EPM7128AELC84-10N vs EPM7128SLC84-10 Comparison
Detailed side-by-side comparison of EPM7128AELC84-10N by Intel and EPM7128SLC84-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128AELC84-10N
EPM7128AELC84-10N - MAX 7000A CPLD, 128 Macro, 10ns, 84-PLCC | Intel
EPM7128AELC84-10N β ActiveIntel
EPM7128SLC84-10
EPM7128SLC84-10 - MAX 7000 CPLD, 128 Macro, 68 I/O, 10ns | Intel
EPM7128SLC84-10 ObsoleteSpecification Comparison
| Parameter | EPM7128AELC84-10N | EPM7128SLC84-10 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.45 | $9.75 |
| Family | MAX 7000A | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | β |
| Usable Gates | 2,500 | β |
| Propagation Delay (tPD) | 10 ns | β |
| User I/O Pins | 68 | β |
| Supply Voltage (VCCINT) | 3.3 V | 5 V |
| Maximum Internal Frequency (fCNT) | 147.1 MHz | β |
| Process Technology | 0.30 Β΅m CMOS EEPROM | β |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | β |
| MultiVolt I/O Interface | 2.5 V / 3.3 V / 5 V mixed | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| Package | 84-pin PLCC (J-Lead) | PLCC-84 (J-lead) |
| Mounting Type | Surface Mount / Through-Hole socket | Surface Mount (J-bend) |
| RoHS Status | Compliant | Non-compliant (contains lead in PLCC) |
| Configuration Memory | Non-volatile EEPROM | β |
| Power-Up Speed | Instant-on (no boot PROM required) | β |
| Macrocells | β | 128 |
| Logic Gates | β | 2500 |
| User I/Os | β | 68 |
| Total Package Pins | β | 84 |
| Propagation Delay (tpd) | β | 10 ns |
| Maximum Operating Frequency | β | 125 MHz |
| Internal Frequency | β | 250 MHz |
| MultiVolt I/O Support | β | 2.5 V / 3.3 V / 5 V |
| Program Memory Type | β | EEPROM (in-system programmable) |
| JTAG (IEEE 1149.1) | β | Yes |
| MSL Level | β | [DATA_NEEDED: MSL level] |