EPM7128AETC100-5N vs EPM7128AETC100-10N Comparison
Detailed side-by-side comparison of EPM7128AETC100-5N by Intel and EPM7128AETC100-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128AETC100-5N
EPM7128AETC100-5N - 128-Macrocell MAX 7000A CPLD, 5ns | Intel / Altera
EPM7128AETC100-5N β ActiveIntel
EPM7128AETC100-10N
EPM7128AETC100-10N - MAX 7000AE 128-Macrocell CPLD | Intel | TQFP-100
EPM7128AETC100-10N ObsoleteSpecification Comparison
| Parameter | EPM7128AETC100-5N | EPM7128AETC100-10N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $6.85 | $9.95 |
| Family | MAX 7000A | MAX 7000AE |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | 128 |
| User I/Os | 84 | 84 |
| Logic Gates (typical) | 2,500 | β |
| Pin-to-Pin Logic Delay (tPD) | 5 ns | β |
| Maximum Operating Frequency | 192.3 MHz | β |
| Core Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Bank Supply Voltage (VCCIO) | 3.3 V or 2.5 V | β |
| 5V Tolerant Inputs | Yes (when VCCIO = 3.3 V) | β |
| Programmable Logic Type | EEPROM-based, in-system programmable | β |
| Programming Interface | JTAG (IEEE Std. 1149.1) | β |
| Package | 100-pin TQFP | TQFP-100 |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| RoHS Status | Compliant | β |
| Series | β | EPM7128AE |
| Usable Gates | β | 2500 |
| Logic Array Blocks | β | 16 |
| Supply Voltage (Core) | β | 3.3 V |
| I/O Tolerance | β | 5.0 V tolerant |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Speed Grade | β | -10 |
| Maximum Frequency | β | [DATA_NEEDED: maximum toggle frequency] |
| Programming | β | JTAG (IEEE 1149.1) ISP / EEPROM |
| Lead-Free / RoHS | β | Yes (N suffix) |
| Process Technology | β | CMOS EEPROM |
| Architecture | β | Multiple Array MatriX (MAX) - 2nd generation |
| PCI Compliance | β | Yes (33 MHz, -10 grade per PCI SIG 2.2) |