EPM7128AETC100-5N vs EPM7256AETC100-5N Comparison
Detailed side-by-side comparison of EPM7128AETC100-5N by Intel and EPM7256AETC100-5N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128AETC100-5N
EPM7128AETC100-5N - 128-Macrocell MAX 7000A CPLD, 5ns | Intel / Altera
EPM7128AETC100-5N β ActiveAltera
EPM7256AETC100-5N
EPM7256AETC100-5N - 256-Macro MAX 7000A CPLD, 5ns TQFP-100
EPM7256AETC100-5N β Last Time BuySpecification Comparison
| Parameter | EPM7128AETC100-5N | EPM7256AETC100-5N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $6.85 | $9.75 |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | β |
| User I/Os | 84 | 84 |
| Logic Gates (typical) | 2,500 | β |
| Pin-to-Pin Logic Delay (tPD) | 5 ns | β |
| Maximum Operating Frequency | 192.3 MHz | β |
| Core Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Bank Supply Voltage (VCCIO) | 3.3 V or 2.5 V | β |
| 5V Tolerant Inputs | Yes (when VCCIO = 3.3 V) | β |
| Programmable Logic Type | EEPROM-based, in-system programmable | β |
| Programming Interface | JTAG (IEEE Std. 1149.1) | β |
| Package | 100-pin TQFP | TQFP-100 (1.0 mm pitch, 14x14 mm) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| RoHS Status | Compliant | Compliant (lead-free) |
| Series | β | MAX 7000AE |
| Macro Cells | β | 256 |
| Usable Gates | β | 5000 (range 600 to 10000) |
| Logic Array Blocks (LABs) | β | 16 |
| Pin-to-Pin Delay (tPD) | β | 5.0 ns |
| Counter Frequency (fCNT) | β | up to 227.3 MHz |
| Supply Voltage (VCCINT) | β | 3.3 V |
| MultiVolt I/O Support | β | 2.5 V / 3.3 V / 5.0 V |
| Program Memory | β | Internal EEPROM |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG) |
| MSL Level | β | 3 (168 hours) |
| Process Technology | β | CMOS, EEPROM-based |
| Security Bit | β | Programmable |