EPM7128AETC100-7N vs EPM7128AETC100-5N Comparison
Detailed side-by-side comparison of EPM7128AETC100-7N by Altera and EPM7128AETC100-5N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128AETC100-5N - 128-Macrocell MAX 7000A CPLD, 5ns | Intel / Altera
EPM7128AETC100-5N β ActiveSpecification Comparison
| Parameter | EPM7128AETC100-7N | EPM7128AETC100-5N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $31.80 | $6.85 |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD - Complex Programmable Logic Device |
| Macro Cells | 128 | β |
| Usable Gates | 2,500 | β |
| Logic Array Blocks (LABs) | 4 | β |
| User I/Os | 84 | 84 |
| Propagation Delay (tpd) | 7.5 ns | β |
| Counter Frequency (max) | 129.9 MHz | β |
| Internal Frequency (max) | 250 MHz | β |
| Core Supply Voltage | 3.3 V | β |
| Logic Family | CMOS | β |
| Pin Count | 100 | β |
| Package | 100-TQFP | 100-pin TQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0 C to +70 C (Commercial) | 0C to +70C (commercial) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE Std. 1149.1) |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant |
| Process Technology | 0.30 Β΅m EEPROM CMOS | β |
| Macrocells | β | 128 |
| Logic Gates (typical) | β | 2,500 |
| Pin-to-Pin Logic Delay (tPD) | β | 5 ns |
| Maximum Operating Frequency | β | 192.3 MHz |
| Core Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Bank Supply Voltage (VCCIO) | β | 3.3 V or 2.5 V |
| 5V Tolerant Inputs | β | Yes (when VCCIO = 3.3 V) |
| Programmable Logic Type | β | EEPROM-based, in-system programmable |