EPM7128AETC144-10 vs EPM7128AETC144-7N Comparison
Detailed side-by-side comparison of EPM7128AETC144-10 by Altera and EPM7128AETC144-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128AETC144-10
EPM7128AETC144-10 - 128-Macrocell MAX 7000A CPLD, 10ns TQFP-144
EPM7128AETC144-10 NrndAltera
EPM7128AETC144-7N
EPM7128AETC144-7N - MAX 7000A CPLD, 128 Macros, 144-TQFP | Intel / Altera
EPM7128AETC144-7N β ActiveSpecification Comparison
| Parameter | EPM7128AETC144-10 | EPM7128AETC144-7N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $21.70 | $39.82 |
| Family | MAX 7000A | MAX 7000A |
| Macrocells | 128 | β |
| Usable Gates | 2,500 | β |
| Logic Array Blocks (LABs) | 8 | β |
| Maximum User I/Os | 36 | β |
| Pin-to-pin Logic Delay (tPD) | 10 ns | β |
| Maximum Internal Counter Frequency | 98 MHz | β |
| Supply Voltage (Core) | 3.3 V | β |
| I/O Voltage Tolerance | 2.5 V / 3.3 V / 5 V | β |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Package | 144-pin TQFP (also referred to as LQFP-144) | 144-pin TQFP |
| Programming Interface | JTAG (IEEE Std. 1149.1) and ByteBlaster | β |
| Non-volatile Memory | EEPROM, instant-on | β |
| Global Clocks / Global OE | 2 / 2 | β |
| Mounting Type | Surface Mount | Surface Mount |
| MSL Level | MSL 3 (per JEDEC J-STD-020) | β |
| RoHS Status | [DATA_NEEDED: rohs status from manufacturer] | Compliant |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Gates | β | 2500 (2.5K gates) |
| Macro Cells | β | 128 |
| User I/Os | β | 36 (in 144-pin TQFP) |
| Maximum Operating Frequency | β | 129.9 MHz |
| Pin-to-Pin Delay | β | 7.5 ns |
| Propagation Delay (tpd) | β | 7.5 ns |
| Supply Voltage (VCCINT) | β | 3.3 V |
| Process Technology | β | CMOS, EEPROM-based |
| Programmability | β | In-System Programmable (ISP) via JTAG |
| Boundary-Scan Test | β | IEEE Std 1149.1 (JTAG) |
| Pin-Compatible With | β | MAX 7000S 5.0V family (144-pin TQFP) |
| Lead-Free | β | Yes |