EPM7128AETC144-7N vs EPM7128AETC144-10 Comparison
Detailed side-by-side comparison of EPM7128AETC144-7N by Altera and EPM7128AETC144-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128AETC144-7N
EPM7128AETC144-7N - MAX 7000A CPLD, 128 Macros, 144-TQFP | Intel / Altera
EPM7128AETC144-7N β ActiveAltera
EPM7128AETC144-10
EPM7128AETC144-10 - 128-Macrocell MAX 7000A CPLD, 10ns TQFP-144
EPM7128AETC144-10 NrndSpecification Comparison
| Parameter | EPM7128AETC144-7N | EPM7128AETC144-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $39.82 | $21.70 |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Logic Gates | 2500 (2.5K gates) | β |
| Macro Cells | 128 | β |
| User I/Os | 36 (in 144-pin TQFP) | β |
| Maximum Operating Frequency | 129.9 MHz | β |
| Pin-to-Pin Delay | 7.5 ns | β |
| Propagation Delay (tpd) | 7.5 ns | β |
| Supply Voltage (VCCINT) | 3.3 V | β |
| Process Technology | CMOS, EEPROM-based | β |
| Programmability | In-System Programmable (ISP) via JTAG | β |
| Boundary-Scan Test | IEEE Std 1149.1 (JTAG) | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| Package | 144-pin TQFP | 144-pin TQFP (also referred to as LQFP-144) |
| Mounting Type | Surface Mount | Surface Mount |
| Pin-Compatible With | MAX 7000S 5.0V family (144-pin TQFP) | β |
| RoHS Status | Compliant | [DATA_NEEDED: rohs status from manufacturer] |
| Lead-Free | Yes | β |
| Macrocells | β | 128 |
| Usable Gates | β | 2,500 |
| Logic Array Blocks (LABs) | β | 8 |
| Maximum User I/Os | β | 36 |
| Pin-to-pin Logic Delay (tPD) | β | 10 ns |
| Maximum Internal Counter Frequency | β | 98 MHz |
| Supply Voltage (Core) | β | 3.3 V |
| I/O Voltage Tolerance | β | 2.5 V / 3.3 V / 5 V |
| Programming Interface | β | JTAG (IEEE Std. 1149.1) and ByteBlaster |
| Non-volatile Memory | β | EEPROM, instant-on |
| Global Clocks / Global OE | β | 2 / 2 |
| MSL Level | β | MSL 3 (per JEDEC J-STD-020) |