EPM7128AETI100-7 vs EPM7128AET1100-7 Comparison
Detailed side-by-side comparison of EPM7128AETI100-7 by Altera and EPM7128AET1100-7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
EPM7128AETI100-7 ObsoleteSpecification Comparison
| Parameter | EPM7128AETI100-7 | EPM7128AET1100-7 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $30.10 | $16.40 |
| Family | MAX 7000A | MAX 7000A (MAX 7000AE) |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| User I/Os | 84 | β |
| Logic Blocks (LABs) | 8 | β |
| Pin-to-Pin Delay (tPD) | 7.5 ns | β |
| Maximum Counter Frequency | 129.9 MHz | β |
| Supply Voltage - Core (VCCINT) | 3.3 V | β |
| I/O Bank Supply (VCCIO) | 2.5 V / 3.3 V / 5 V (MultiVolt) | β |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | EEPROM (non-volatile, instant-on) |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | β |
| Global Clock Inputs | 4 dedicated | β |
| Package | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) | TQFP-100 |
| Operating Temperature | -40 C to +85 C (Industrial) | -40C to +85C (industrial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: confirm RoHS for non-N suffix] | ROHS3 Compliant |
| Lead-Free Version (MPN Suffix) | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) | β |
| User I/O Pins | β | 84 |
| Logic Elements / LABs | β | [DATA_NEEDED: LAB count for 7128A] |
| Speed Grade | β | -7 (5 ns pin-to-pin) |
| Supply Voltage VCC | β | 5.0 V (typical) |
| I/O Voltage Tolerance | β | 3.3 V / 5.0 V |
| Programming Interface | β | IEEE 1149.1 JTAG / ByteBlaster |
| MSL Level | β | 3 (168 hours, per JEDEC J-STD-020) |
| Lead-Free | β | Yes |
| Process Technology | β | CMOS, EEPROM-based |