EPM7128AETI100-7 vs EPM7128ATC100-10 Comparison
Detailed side-by-side comparison of EPM7128AETI100-7 by Altera and EPM7128ATC100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
EPM7128AETI100-7 ObsoleteAltera
EPM7128ATC100-10 - MAX 7000A CPLD, 128 Macrocells, 10ns TQFP-100 | Altera
EPM7128ATC100-10 ObsoleteSpecification Comparison
| Parameter | EPM7128AETI100-7 | EPM7128ATC100-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $30.10 | $4.95 |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2.5K |
| User I/Os | 84 | β |
| Logic Blocks (LABs) | 8 | β |
| Pin-to-Pin Delay (tPD) | 7.5 ns | β |
| Maximum Counter Frequency | 129.9 MHz | β |
| Supply Voltage - Core (VCCINT) | 3.3 V | β |
| I/O Bank Supply (VCCIO) | 2.5 V / 3.3 V / 5 V (MultiVolt) | β |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | β |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | β |
| Global Clock Inputs | 4 dedicated | β |
| Package | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) | 100-pin TQFP (TC100) |
| Operating Temperature | -40 C to +85 C (Industrial) | 0C to +70C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: confirm RoHS for non-N suffix] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free Version (MPN Suffix) | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) | β |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Architecture | β | Multiple Array MatriX (MAX) |
| Logic Array Blocks (LABs) | β | 4 |
| User I/O Pins | β | 68 |
| Pin-to-Pin Logic Delay | β | 4.5 ns |
| Counter Frequency (max) | β | 227.3 MHz |
| Speed Grade | β | -10 (10 ns) |
| Core Supply Voltage | β | 3.3 V |
| I/O Logic Level Support | β | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Program Memory | β | EEPROM (non-volatile) |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG) |