EPM7128AETI100-7N vs EPM7128AETC100-10N Comparison

Detailed side-by-side comparison of EPM7128AETI100-7N by Altera and EPM7128AETC100-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7128AETI100-7N EPM7128AETC100-10N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $28.50 $9.95
Series MAX 7000A EPM7128AE
Family MAX 7000A CPLD MAX 7000AE
Macro Cells 128 β€”
Number of Usable Gates 2,500 β€”
Number of I/O 84 β€”
Number of Logic Array Blocks (LABs) 8 β€”
Propagation Delay (tPD max) 7 ns β€”
Maximum Operating Frequency (fCNT) 129.9 MHz β€”
Supply Voltage (VCCINT) 3.0 V to 3.6 V β€”
I/O Bank Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) β€”
Process Technology CMOS EEPROM CMOS EEPROM
Package 100-pin TQFP (14x14 mm) TQFP-100
Mounting Type Surface Mount Surface Mount
Operating Temperature -40C to +85C (Industrial) 0C to +70C (commercial)
In-System Programmability Yes (JTAG IEEE 1149.1) β€”
RoHS Status Compliant β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
Macrocells β€” 128
Usable Gates β€” 2500
Logic Array Blocks β€” 16
User I/Os β€” 84
Supply Voltage (Core) β€” 3.3 V
I/O Tolerance β€” 5.0 V tolerant
Pin-to-Pin Delay (tPD) β€” 10 ns
Speed Grade β€” -10
Maximum Frequency β€” [DATA_NEEDED: maximum toggle frequency]
Programming β€” JTAG (IEEE 1149.1) ISP / EEPROM
Lead-Free / RoHS β€” Yes (N suffix)
Architecture β€” Multiple Array MatriX (MAX) - 2nd generation
PCI Compliance β€” Yes (33 MHz, -10 grade per PCI SIG 2.2)

Datasheets & Resources

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