EPM7128AETI100-7N vs EPM7256AETI100-7N Comparison
Detailed side-by-side comparison of EPM7128AETI100-7N by Altera and EPM7256AETI100-7N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128AETI100-7N - MAX 7000A CPLD 128 Macro 84 I/O | Intel/Altera
EPM7128AETI100-7N ObsoleteIntel
EPM7256AETI100-7N - 256-MacroCell MAX 7000A CPLD, 100TQFP | Intel
EPM7256AETI100-7N β Last Time BuySpecification Comparison
| Parameter | EPM7128AETI100-7N | EPM7256AETI100-7N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $28.50 | $34.20 |
| Series | MAX 7000A | β |
| Family | MAX 7000A CPLD | MAX 7000A |
| Macro Cells | 128 | β |
| Number of Usable Gates | 2,500 | β |
| Number of I/O | 84 | β |
| Number of Logic Array Blocks (LABs) | 8 | β |
| Propagation Delay (tPD max) | 7 ns | β |
| Maximum Operating Frequency (fCNT) | 129.9 MHz | β |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | β |
| I/O Bank Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) | β |
| Process Technology | CMOS EEPROM | β |
| Package | 100-pin TQFP (14x14 mm) | 100-pin TQFP (TQ100, 14x14 mm, 0.5 mm pitch) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | β |
| RoHS Status | Compliant | Compliant |
| Device Type | β | CPLD - Complex Programmable Logic Device |
| Macrocells | β | 256 |
| Usable Gates | β | 5,000 |
| Maximum User I/O | β | 84 |
| Logic Elements / Blocks | β | 16 Logic Array Blocks |
| Maximum Operating Frequency | β | 126.6 MHz |
| Propagation Delay (tPD) | β | 7.5 ns |
| Core Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Supply Voltage (VCCIO) | β | 3.3 V |
| Technology | β | CMOS, EEPROM-based configuration |
| Programmability | β | In-system programmable via JTAG (IEEE 1149.1) |
| MSL Level | β | 3 (168 hours) |