EPM7128ATC100-10 vs EPM7128STI100-10N Comparison

Detailed side-by-side comparison of EPM7128ATC100-10 by Altera and EPM7128STI100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM7128ATC100-10

EPM7128ATC100-10 - MAX 7000A CPLD, 128 Macrocells, 10ns TQFP-100 | Altera

EPM7128ATC100-10 Obsolete
Altera
EPM7128STI100-10N

EPM7128STI100-10N - 128-Macrocell CPLD, 10ns, 100-pin TQFP | Altera

EPM7128STI100-10N Obsolete

Specification Comparison

Parameter EPM7128ATC100-10 EPM7128STI100-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $4.95 $9.85
Product Type CPLD (Complex Programmable Logic Device) β€”
Family MAX 7000A MAX 7000S
Architecture Multiple Array MatriX (MAX) CMOS EEPROM-based CPLD
Macrocells 128 128
Logic Array Blocks (LABs) 4 8
Usable Gates 2.5K 2,500 (up to 5,000 family max)
User I/O Pins 68 β€”
Pin-to-Pin Logic Delay 4.5 ns β€”
Counter Frequency (max) 227.3 MHz β€”
Speed Grade -10 (10 ns) β€”
Core Supply Voltage 3.3 V β€”
I/O Logic Level Support 5.0 V / 3.3 V / 2.5 V (MultiVolt) β€”
Program Memory EEPROM (non-volatile) β€”
In-System Programmability Yes (IEEE 1149.1 JTAG) Yes (JTAG IEEE 1149.1)
Package 100-pin TQFP (TC100) 100-pin TQFP
Mounting Type Surface Mount Surface Mount
Operating Temperature 0C to +70C (commercial) -40C to +85C (Industrial)
RoHS Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Maximum User I/O β€” 84
Pin-to-Pin Logic Delay (tPD) β€” 10 ns
Maximum Counter Frequency β€” 175.4 MHz
Supply Voltage (VCC) β€” 5 V
JTAG Boundary-Scan β€” Yes (BST)
MSL Level β€” [DATA_NEEDED: MSL level]
Open-Drain I/O Option β€” Available (per MAX 7000A feature set)

Datasheets & Resources

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