EPM7128ATC100-7F vs EPM7128AETC100-10N Comparison
Detailed side-by-side comparison of EPM7128ATC100-7F by Altera and EPM7128AETC100-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128ATC100-7F
EPM7128ATC100-7F - 128-Macrocell MAX 7000A CPLD, 7.5ns, 100-TQFP | Intel / Altera
EPM7128ATC100-7F NrndIntel
EPM7128AETC100-10N
EPM7128AETC100-10N - MAX 7000AE 128-Macrocell CPLD | Intel | TQFP-100
EPM7128AETC100-10N ObsoleteSpecification Comparison
| Parameter | EPM7128ATC100-7F | EPM7128AETC100-10N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.85 | $9.95 |
| Family | MAX 7000A | MAX 7000AE |
| Device | EPM7128A | β |
| Logic Elements / Macrocells | 128 macrocells | β |
| Logic Array Blocks (LABs) | 8 | β |
| Usable Gates | 2.5K | 2500 |
| User I/O Pins | 84 (per MicrochipUSA) / 100 (per MAX 7000A datasheet range) | β |
| Propagation Delay (tPD) | 7.5 ns | β |
| Maximum Internal Frequency (fMAX) | 116.3 MHz | β |
| Supply Voltage - Internal | 3.0 V to 3.6 V (nominal 3.3 V) | β |
| I/O Voltage | 2.5 V / 3.3 V (MultiVolt) | β |
| Programmable Type | EEPROM (in-system programmable, non-volatile) | β |
| JTAG Support | IEEE Std 1149.1 boundary-scan + ISP | β |
| Package | 100-pin TQFP (14x14 mm) | TQFP-100 |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Process Technology | CMOS, EEPROM configuration | CMOS EEPROM |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Series | β | EPM7128AE |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocells | β | 128 |
| Logic Array Blocks | β | 16 |
| User I/Os | β | 84 |
| Supply Voltage (Core) | β | 3.3 V |
| I/O Tolerance | β | 5.0 V tolerant |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Speed Grade | β | -10 |
| Maximum Frequency | β | [DATA_NEEDED: maximum toggle frequency] |
| Programming | β | JTAG (IEEE 1149.1) ISP / EEPROM |
| Lead-Free / RoHS | β | Yes (N suffix) |
| Architecture | β | Multiple Array MatriX (MAX) - 2nd generation |
| PCI Compliance | β | Yes (33 MHz, -10 grade per PCI SIG 2.2) |