EPM7128ATC100-7F vs EPM7128AETC100-7N Comparison
Detailed side-by-side comparison of EPM7128ATC100-7F by Altera and EPM7128AETC100-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128ATC100-7F
EPM7128ATC100-7F - 128-Macrocell MAX 7000A CPLD, 7.5ns, 100-TQFP | Intel / Altera
EPM7128ATC100-7F NrndAltera
EPM7128AETC100-7N
EPM7128AETC100-7N - MAX 7000A CPLD, 128 MC, 7.5ns, 100-TQFP | Altera
EPM7128AETC100-7N NrndSpecification Comparison
| Parameter | EPM7128ATC100-7F | EPM7128AETC100-7N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.85 | $31.80 |
| Family | MAX 7000A | MAX 7000A |
| Device | EPM7128A | β |
| Logic Elements / Macrocells | 128 macrocells | β |
| Logic Array Blocks (LABs) | 8 | 4 |
| Usable Gates | 2.5K | 2,500 |
| User I/O Pins | 84 (per MicrochipUSA) / 100 (per MAX 7000A datasheet range) | β |
| Propagation Delay (tPD) | 7.5 ns | β |
| Maximum Internal Frequency (fMAX) | 116.3 MHz | β |
| Supply Voltage - Internal | 3.0 V to 3.6 V (nominal 3.3 V) | β |
| I/O Voltage | 2.5 V / 3.3 V (MultiVolt) | β |
| Programmable Type | EEPROM (in-system programmable, non-volatile) | β |
| JTAG Support | IEEE Std 1149.1 boundary-scan + ISP | β |
| Package | 100-pin TQFP (14x14 mm) | 100-TQFP |
| Operating Temperature | -40C to +85C (industrial) | 0 C to +70 C (Commercial) |
| Process Technology | CMOS, EEPROM configuration | 0.30 Β΅m EEPROM CMOS |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Device Type | β | CPLD - Complex Programmable Logic Device |
| Macro Cells | β | 128 |
| User I/Os | β | 84 |
| Propagation Delay (tpd) | β | 7.5 ns |
| Counter Frequency (max) | β | 129.9 MHz |
| Internal Frequency (max) | β | 250 MHz |
| Core Supply Voltage | β | 3.3 V |
| Logic Family | β | CMOS |
| Pin Count | β | 100 |
| Programming Interface | β | JTAG (IEEE 1149.1) / ISP |