EPM7128ELC84-10 vs EPM7128SLC8410 Comparison
Detailed side-by-side comparison of EPM7128ELC84-10 by Intel and EPM7128SLC8410 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7128ELC84-10 | EPM7128SLC8410 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.20 | $9.75 |
| Family | MAX 7000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 128 | 128 |
| Equivalent Logic Gates | [DATA_NEEDED: equivalent gate count from datasheet] | β |
| User I/Os | 68 | β |
| Dedicated Inputs | 12 | β |
| Operating Voltage (VCCINT/VCClO) | 5 V | β |
| Pin-to-Pin Delay (tPD) | 10 ns | β |
| Counter Frequency (fCNT) | [DATA_NEEDED: fCNT from datasheet] | β |
| Package | 84-pin PLCC (J-Lead) | 84-pin PLCC (J-lead) |
| Mounting Type | Surface Mount / Socket | Surface Mount (PLCC socket or direct solder) |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Technology | EEPROM-based CMOS | β |
| Programming Interface | IEEE 1149.1 (JTAG) ISP | β |
| In-System Programmable | Yes | β |
| RoHS Status | [DATA_NEEDED: RoHS status from datasheet] | [DATA_NEEDED: RoHS status - not stated in verified data] |
| Lead-Free | [DATA_NEEDED: lead-free status from datasheet] | β |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Elements / Gates | β | 2500 usable gates |
| User I/O Pins | β | 68 |
| Number of Logic Array Blocks (LABs) | β | 8 |
| Propagation Delay (tPD) | β | 10 ns |
| Setup Time (tSU) | β | 7 ns |
| Maximum Operating Frequency | β | 125 MHz (counter) |
| Supply Voltage (VCCINT) | β | 4.75 V to 5.25 V (5 V nominal) |
| I/O Voltage (MultiVolt) | β | 2.5 V / 3.3 V / 5.0 V |
| Program Memory Type | β | EEPROM (in-system programmable) |
| JTAG Support | β | IEEE Std 1149.1 boundary-scan |