EPM7128ELC84-12 vs EPM7096LC84-15 Comparison
Detailed side-by-side comparison of EPM7128ELC84-12 by Altera and EPM7096LC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7128ELC84-12 | EPM7096LC84-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.40 | $9.85 |
| Family | MAX 7000 (MAX 7000E series) | MAX 7000 |
| Logic Family | CMOS, EEPROM-based | β |
| Usable Gates | 2,500 | 1,800 |
| Macrocells | 128 | β |
| Logic Array Blocks (LABs) | 8 | 4 |
| User I/Os | 84 | β |
| Propagation Delay (tpd1) | 12 ns | β |
| Internal Global Clock Frequency | 90.9 MHz | β |
| Setup Time | 4.5 ns | β |
| Supply Voltage (VCCINT / VCCIO) | 5 V (4.75 V to 5.25 V) | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Package | 84-pin PLCC (J-Lead, QCCJ) | β |
| Mounting Type | Surface Mount (PLCC socket compatible) | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | IEEE Std. 1149.1 JTAG |
| Pin Count | 84 | β |
| RoHS Status | Non-compliant (legacy 5V part, SnPb finish) | [DATA_NEEDED: RoHS compliance status] |
| Series | β | MAX 7000 (second-generation MAX architecture) |
| Macro Cells | β | 96 |
| Pin-to-Pin Propagation Delay (tPD) | β | 15 ns |
| Maximum Operating Frequency | β | 76.9 MHz |
| User I/O Pins | β | 68 (36 per LAB, [DATA_NEEDED: exact LAB-level split]) |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V |
| Programmable Type | β | EE PLD (in-system programmable via JTAG) |
| Package / Case | β | 84-PLCC (J-Lead) |
| Supplier Device Package | β | 84-PLCC (29.31 x 29.31 mm) |
| Data Retention | β | [DATA_NEEDED: data retention years] |
| Erase/Program Endurance | β | [DATA_NEEDED: erase/program cycle count] |