EPM7128SLC84-10 vs EPM7128SLI84-10N Comparison
Detailed side-by-side comparison of EPM7128SLC84-10 by Intel and EPM7128SLI84-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128SLC84-10
EPM7128SLC84-10 - MAX 7000 CPLD, 128 Macro, 68 I/O, 10ns | Intel
EPM7128SLC84-10 ObsoleteAltera
EPM7128SLI84-10N
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
EPM7128SLI84-10N NrndSpecification Comparison
| Parameter | EPM7128SLC84-10 | EPM7128SLI84-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $8.45 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 128 | β |
| Logic Gates | 2500 | β |
| User I/Os | 68 | 68 |
| Total Package Pins | 84 | β |
| Package | PLCC-84 (J-lead) | 84-pin PLCC (J-Lead) |
| Propagation Delay (tpd) | 10 ns | β |
| Maximum Operating Frequency | 125 MHz | β |
| Internal Frequency | 250 MHz | β |
| Supply Voltage (VCCINT) | 5 V | 4.75 V to 5.25 V (5 V typical) |
| MultiVolt I/O Support | 2.5 V / 3.3 V / 5 V | β |
| Program Memory Type | EEPROM (in-system programmable) | β |
| JTAG (IEEE 1149.1) | Yes | β |
| Operating Temperature | 0C to +70C (Commercial) | -40 C to +85 C (Industrial) |
| Mounting Type | Surface Mount (J-bend) | Surface Mount |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | Non-compliant (contains lead in PLCC) | [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration] |
| Logic Cells / Macro Cells | β | 128 macro cells |
| Usable Gates | β | 2,500 |
| Number of Logic Elements / Blocks | β | 16 Logic Array Blocks (LABs) |
| Propagation Delay (tPD) | β | 10 ns |
| Maximum Frequency (fMAX) | β | 125 MHz |
| I/O Voltage Tolerance | β | 3.3 V / 5 V MultiVolt I/O |
| Process Technology | β | CMOS EEPROM |
| Programmability | β | In-system programmable (ISP), non-volatile EEPROM |
| Boundary-Scan (JTAG) | β | IEEE Std 1149.1 compliant |
| Lead-Free | β | [DATA_NEEDED: lead-free per latest Intel/Altera declaration] |