EPM7128SLC84-10 vs EPM7160SLC84-10 Comparison
Detailed side-by-side comparison of EPM7128SLC84-10 by Intel and EPM7160SLC84-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7128SLC84-10 | EPM7160SLC84-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $35.77 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 128 | 160 |
| Logic Gates | 2500 | β |
| User I/Os | 68 | β |
| Total Package Pins | 84 | β |
| Package | PLCC-84 (J-lead) | 84-Pin PLCC (J-Lead) |
| Propagation Delay (tpd) | 10 ns | β |
| Maximum Operating Frequency | 125 MHz | 100 MHz |
| Internal Frequency | 250 MHz | β |
| Supply Voltage (VCCINT) | 5 V | β |
| MultiVolt I/O Support | 2.5 V / 3.3 V / 5 V | β |
| Program Memory Type | EEPROM (in-system programmable) | β |
| JTAG (IEEE 1149.1) | Yes | β |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Mounting Type | Surface Mount (J-bend) | Surface Mount |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | Non-compliant (contains lead in PLCC) | [DATA_NEEDED: RoHS status] |
| Logic Array Blocks (LABs) | β | 4 |
| Maximum User I/O Pins | β | 64 |
| Usable Gates | β | 3,200 |
| Propagation Delay (tPD) | β | 10 ns |
| Supply Voltage (VCCINT/VCCIO) | β | 5.0 V |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG, 5.0 V) |
| Technology | β | EEPROM-based CMOS |
| JTAG Boundary Scan | β | Yes (IEEE Std. 1149.1 compliant) |