EPM7128SLC84-15 vs EPM7160SLC84-15 Comparison
Detailed side-by-side comparison of EPM7128SLC84-15 by Intel and EPM7160SLC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128SLC84-15
EPM7128SLC84-15 - 128-Macrocell MAX 7000S CPLD, 84-PLCC | Intel / Altera
EPM7128SLC84-15 β Last Time BuyAltera
EPM7160SLC84-15
EPM7160SLC84-15 - MAX 7000 CPLD, 160 Macrocells, 15ns | Altera
EPM7160SLC84-15 ObsoleteSpecification Comparison
| Parameter | EPM7128SLC84-15 | EPM7160SLC84-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.40 | $10.80 |
| Family | MAX 7000S | MAX 7000 |
| Device Type | CPLD - Complex Programmable Logic Device | β |
| Macrocells | 128 | 160 |
| Usable Gates | 2,500 | 3,200 |
| User I/Os | 68 (in 84-PLCC) | β |
| Package | 84-Pin PLCC (J-Lead, J84) | β |
| Speed Grade | -15 (15 ns pin-to-pin delay) | β |
| Propagation Delay (tPD) | 15 ns | β |
| Maximum Internal Frequency (fMAX) | 76.9 MHz | β |
| Logic Family / Process | CMOS, 5V, EEPROM | β |
| Supply Voltage (VCCINT) | 5 V | β |
| I/O Standard Support | 5.0 V TTL/CMOS (multi-volt I/O compatible with 3.3V) | β |
| Programming Interface | JTAG (IEEE Std. 1149.1), in-system programmable | JTAG (IEEE 1149.1) in-system programmable |
| Configuration Memory | Non-volatile EEPROM (instant-on, no boot PROM) | β |
| Operating Temperature | 0C to +70C (commercial) | 0 C to 70 C |
| RoHS Status | Non-RoHS (legacy 5V part) | Not RoHS compliant (contains lead, SnPb finish typical) |
| Mounting Type | Surface Mount / Socketed (PLCC-84 socket) | Surface Mount (PLCC socket or direct solder) |
| Maximum Propagation Delay | β | 15 ns |
| Maximum User I/O Pins | β | 64 |
| Supply Voltage (VCCINT/VCIO) | β | 4.75 V to 5.25 V (5 V nominal) |
| I/O Logic Level | β | Configurable 3.3 V or 5 V |
| Technology | β | CMOS, EEPROM configuration |
| Package Type | β | PLCC-84 (PQCC84, JEDEC S-PQCC-J84) |
| Terminal Pitch | β | 1.270 mm |
| Lifecycle | β | Obsolete / last-time-buy (per Altera/Intel PDN) |