EPM7128SLI84-10N vs EPM7128ELI84-20 Comparison
Detailed side-by-side comparison of EPM7128SLI84-10N by Altera and EPM7128ELI84-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128SLI84-10N
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
EPM7128SLI84-10N NrndIntel
EPM7128ELI84-20
EPM7128ELI84-20 - 128-Macrocell CPLD, 20ns, 84-PLCC | Intel / Altera
EPM7128ELI84-20 β Last Time BuySpecification Comparison
| Parameter | EPM7128SLI84-10N | EPM7128ELI84-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.45 | $7.95 |
| Family | MAX 7000S | MAX 7000 (Classic / MAX 7000B/E) |
| Logic Cells / Macro Cells | 128 macro cells | β |
| Usable Gates | 2,500 | 2,500 |
| Number of Logic Elements / Blocks | 16 Logic Array Blocks (LABs) | β |
| User I/Os | 68 | β |
| Propagation Delay (tPD) | 10 ns | β |
| Maximum Frequency (fMAX) | 125 MHz | β |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V typical) | 5 V (4.75 V to 5.25 V for -20 speed grade) |
| I/O Voltage Tolerance | 3.3 V / 5 V MultiVolt I/O | β |
| Process Technology | CMOS EEPROM | β |
| Programmability | In-system programmable (ISP), non-volatile EEPROM | β |
| Boundary-Scan (JTAG) | IEEE Std 1149.1 compliant | β |
| Package | 84-pin PLCC (J-Lead) | 84-pin PLCC (J-Lead) |
| Mounting Type | Surface Mount | Surface Mount / Socketable (PLCC J-Lead) |
| Operating Temperature | -40 C to +85 C (Industrial) | -40 Β°C to +85 Β°C (Industrial) |
| RoHS Status | [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration] | Compliant (lead-free PLCC variant) |
| Lead-Free | [DATA_NEEDED: lead-free per latest Intel/Altera declaration] | β |
| Device Name | β | EPM7128E |
| Macro Cells | β | 128 |
| Logic Array Blocks (LABs) | β | 8 |
| Maximum User I/Os | β | 68 |
| Pin-to-Pin Delay (tPD) | β | 20 ns |
| Maximum Operating Frequency (fCNT) | β | 62.5 MHz |
| Programming Interface | β | JTAG (IEEE 1149.1) + ISP |
| Technology | β | EEPROM-based CMOS |