EPM7128SLI84-15 vs EPM7128SLI84-10N Comparison
Detailed side-by-side comparison of EPM7128SLI84-15 by Intel and EPM7128SLI84-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128SLI84-15
EPM7128SLI84-15 - 128-Macrocell CPLD, 15ns, PLCC-84 | Altera / Intel
EPM7128SLI84-15 ObsoleteAltera
EPM7128SLI84-10N
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
EPM7128SLI84-10N NrndSpecification Comparison
| Parameter | EPM7128SLI84-15 | EPM7128SLI84-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.40 | $8.45 |
| Family | MAX 7000 | MAX 7000S |
| Series | EPM7128S | β |
| Device Type | EE PLD (CPLD) | β |
| Macrocells | 128 | β |
| Logic Elements | 250 (approx.) | β |
| User I/O Pins | 84 (68 in 84-pin PLCC per some sources) | β |
| Propagation Delay (tpd) | 15 ns | β |
| Supply Voltage (VCCINT) | 4.5 V to 5.5 V | 4.75 V to 5.25 V (5 V typical) |
| I/O Voltage Tolerance | 3.3 V or 5.0 V (configurable) | 3.3 V / 5 V MultiVolt I/O |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Program Memory Type | EEPROM (in-system programmable) | β |
| Package | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) | 84-pin PLCC (J-Lead) |
| Operating Temperature | -40 C to +85 C (Industrial grade, 'I' suffix) | -40 C to +85 C (Industrial) |
| Pin Count | 84 | β |
| Mounting Type | Surface Mount (PLCC socket compatible) | Surface Mount |
| RoHS Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration] |
| Programming Interface | JTAG (IEEE 1149.1) | β |
| Maximum User Flash Endurance | 100 program/erase cycles | β |
| Data Retention | 20 years | β |
| Logic Cells / Macro Cells | β | 128 macro cells |
| Usable Gates | β | 2,500 |
| Number of Logic Elements / Blocks | β | 16 Logic Array Blocks (LABs) |
| User I/Os | β | 68 |
| Propagation Delay (tPD) | β | 10 ns |
| Maximum Frequency (fMAX) | β | 125 MHz |
| Programmability | β | In-system programmable (ISP), non-volatile EEPROM |
| Boundary-Scan (JTAG) | β | IEEE Std 1149.1 compliant |
| Lead-Free | β | [DATA_NEEDED: lead-free per latest Intel/Altera declaration] |