EPM7128SQC100-15 vs EPM7128SQI100-10 Comparison

Detailed side-by-side comparison of EPM7128SQC100-15 by Altera and EPM7128SQI100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM7128SQC100-15 EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 ⚠ Last Time Buy

Specification Comparison

Parameter EPM7128SQC100-15 EPM7128SQI100-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.20 $9.75
Family MAX 7000 MAX 7000S
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Macrocells 128 β€”
Logic Array Blocks (LABs) 4 (16 macrocells each) β€”
User I/Os 84 84
Pin-to-Pin Delay (tPD) 15 ns 10 ns
Maximum Frequency (fMAX) [DATA_NEEDED: fMAX value] β€”
Typical Gate Count 2,500 gates β€”
Supply Voltage (VCCINT) 5 V (5% tolerance) β€”
Programming Technology EEPROM (in-system programmable via JTAG) β€”
JTAG Interface IEEE Std. 1149.1 compliant β€”
Package 100-pin PQFP (Plastic Quad Flat Pack) β€”
Operating Temperature 0C to +70C (Commercial) -40C to +85C (Industrial)
Mounting Type Surface Mount β€”
MSL Level 3 (168 hours) β€”
RoHS Status Non-compliant (SnPb lead finish - legacy PQFP) [DATA_NEEDED: RoHS status not in provided data]
Macro Cells β€” 128
Usable Gates β€” 2,500
Logic Blocks (LABs) β€” 8 (16 macrocells each)
Package Type β€” PQFP-100
Maximum Internal Frequency β€” 125 MHz to 250 MHz
Counter Speed β€” Up to 175.4 MHz
Operating Voltage (VCC) β€” 5 V
Configuration Memory β€” EEPROM (non-volatile)
Program/Erase Cycles β€” 100 minimum
In-System Programming β€” Yes (JTAG IEEE 1149.1)
Logic Family β€” CMOS
I/O Compatibility β€” TTL-compatible, 5V/3.3V multi-voltage

Datasheets & Resources

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