EPM7128SQC100-15 vs EPM7128STC100-10 Comparison

Detailed side-by-side comparison of EPM7128SQC100-15 by Altera and EPM7128STC100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM7128SQC100-15 EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel

EPM7128SQC100-15 ⚠ Last Time Buy
Altera
EPM7128STC100-10

EPM7128STC100-10 - 128-Macro MAX 7000S CPLD, 10ns TQFP-100 | Intel / Altera

EPM7128STC100-10 Obsolete

Specification Comparison

Parameter EPM7128SQC100-15 EPM7128STC100-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.20 $7.10
Family MAX 7000 MAX 7000S
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 128 β€”
Logic Array Blocks (LABs) 4 (16 macrocells each) β€”
User I/Os 84 84
Pin-to-Pin Delay (tPD) 15 ns β€”
Maximum Frequency (fMAX) [DATA_NEEDED: fMAX value] β€”
Typical Gate Count 2,500 gates β€”
Supply Voltage (VCCINT) 5 V (5% tolerance) 5 V
Programming Technology EEPROM (in-system programmable via JTAG) β€”
JTAG Interface IEEE Std. 1149.1 compliant β€”
Package 100-pin PQFP (Plastic Quad Flat Pack) TQFP-100 (C100)
Operating Temperature 0C to +70C (Commercial) 0C to +70C (commercial)
Mounting Type Surface Mount Surface Mount
MSL Level 3 (168 hours) β€”
RoHS Status Non-compliant (SnPb lead finish - legacy PQFP) [DATA_NEEDED: RoHS compliance status not in provided data]
Macro Cells β€” 128
Usable Gates β€” 2,500
Logic Array Blocks β€” 8 (16 macrocells per LAB)
Propagation Delay (tPD) β€” 10 ns
Internal Counter Frequency (fCNT) β€” 100 MHz
Logic Family β€” CMOS
MultiVolt I/O Voltage β€” 3.3 V / 5 V
Pin Count β€” 100
Programmability β€” In-System Programmable (JTAG, IEEE 1149.1), EEPROM

Datasheets & Resources

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