EPM7128SQC100-15 vs EPM7128STC100-15N Comparison
Detailed side-by-side comparison of EPM7128SQC100-15 by Altera and EPM7128STC100-15N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel
EPM7128SQC100-15 β Last Time BuyIntel
EPM7128STC100-15N
EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
EPM7128STC100-15N ObsoleteSpecification Comparison
| Parameter | EPM7128SQC100-15 | EPM7128STC100-15N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.20 | $9.20 |
| Family | MAX 7000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 128 | β |
| Logic Array Blocks (LABs) | 4 (16 macrocells each) | 8 (16 macro cells each) |
| User I/Os | 84 | β |
| Pin-to-Pin Delay (tPD) | 15 ns | β |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX value] | β |
| Typical Gate Count | 2,500 gates | β |
| Supply Voltage (VCCINT) | 5 V (5% tolerance) | β |
| Programming Technology | EEPROM (in-system programmable via JTAG) | β |
| JTAG Interface | IEEE Std. 1149.1 compliant | β |
| Package | 100-pin PQFP (Plastic Quad Flat Pack) | 100-pin TQFP |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Mounting Type | Surface Mount | β |
| MSL Level | 3 (168 hours) | β |
| RoHS Status | Non-compliant (SnPb lead finish - legacy PQFP) | Non-RoHS (legacy SnPb finish typical) |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Usable Gates | β | 2,500 |
| Macro Cells | β | 128 |
| Maximum User I/O | β | 84 |
| Pin-to-Pin Logic Delay (tPD) | β | 15 ns (-15 speed grade) |
| Maximum Internal Frequency | β | 76.9 MHz |
| Supply Voltage (VCC) | β | 5 V (4.75 V to 5.25 V) |
| Supply Voltage (VCCIO) | β | 3.3 V or 5 V (per bank) |
| Technology | β | CMOS EEPROM, in-system programmable |
| JTAG (IEEE 1149.1) | β | Yes - in-system programming |
| Output Options | β | Totem-pole or open-drain (per pin) |
| Dedicated Inputs | β | 4 global inputs |
| Lifecycle Status | β | Obsolete (PDN effective 2017-06-01) |