EPM7128SQC100-7F vs EPM7128SQC100-10N Comparison

Detailed side-by-side comparison of EPM7128SQC100-7F by Altera and EPM7128SQC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7128SQC100-7F EPM7128SQC100-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Active
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $14.95
Family MAX 7000S MAX 7000
Logic Elements / Blocks 8 LABs β€”
Number of Macrocells 128 β€”
Number of Usable Gates 2,500 β€”
Maximum Operating Frequency 125 MHz β€”
Pin-to-Pin Delay (tPD) 7.5 ns β€”
Number of User I/O 84 β€”
Supply Voltage (VCCINT) 4.75 V to 5.25 V (5 V nominal) 5 V (4.75 V to 5.25 V)
Programmable Type In-System Programmable (ISP), EEPROM β€”
JTAG Boundary-Scan Yes (IEEE 1149.1 BST) β€”
Open-Drain Output Option Yes β€”
Operating Temperature 0 Β°C to 70 Β°C (Commercial) -40C to +85C (industrial)
Package 100-pin PQFP (SQC100), surface-mount 100-pin PQFP (BQFP)
Mounting Type Surface Mount Surface Mount
Lead-Free (Pb-Free) Yes (matte-tin, '-F' suffix) β€”
RoHS Status [DATA_NEEDED: confirmed from manufacturer] β€”
Memory Type Non-volatile (EEPROM configuration) β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
Macro Cells β€” 128
Usable Gates β€” 2,500
Logic Array Blocks (LABs) β€” 8 (16 macro cells each)
User I/O Pins β€” 84
Propagation Delay (tPD) β€” 10 ns
Maximum Frequency β€” 100 MHz
I/O Voltage Tolerance β€” 3.3 V or 5 V (MultiVolt interface)
Configuration Memory β€” EEPROM (non-volatile)
Programming Interface β€” JTAG (IEEE Std 1149.1), 4-pin
Lead-Free / RoHS Status β€” Lead-free (N suffix)
Architecture Generation β€” Second-generation MAX

Datasheets & Resources

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