EPM7128SQC100-7N vs EPM7128SQC100-10N Comparison
Detailed side-by-side comparison of EPM7128SQC100-7N by Intel and EPM7128SQC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128SQC100-7N
EPM7128SQC100-7N - MAX 7000 CPLD, 128 Macrocells, 7.5ns, 100-Pin PQFP | Intel (Altera)
EPM7128SQC100-7N ObsoleteAltera
EPM7128SQC100-10N
EPM7128SQC100-10N - MAX 7000 128-Macro-Cell CPLD, 10ns | Altera
EPM7128SQC100-10N β ActiveSpecification Comparison
| Parameter | EPM7128SQC100-7N | EPM7128SQC100-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.10 | $14.95 |
| Family | MAX 7000S | MAX 7000 |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Program Memory Type | EEPROM | β |
| Number of Macrocells | 128 | β |
| Number of Logic Array Blocks | 8 | β |
| Number of Global Clocks | 2 | β |
| Product Terms per Macrocell | 32 | β |
| Usable Gates | 2,500 | 2,500 |
| System Gates | 5,000 (max) | β |
| Maximum User I/Os | 84 | β |
| Pin-to-Pin Delay (tPD) | 7.5 ns | β |
| Counter Speed | 175.4 MHz | β |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | β |
| Operating Voltage (Core) | 5.0 V | β |
| I/O Standard Support | multiVolt (2.5V, 3.3V, 5.0V) | β |
| Package | 100-pin PQFP (QFP-100) | 100-pin PQFP (BQFP) |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) |
| RoHS Status | Compliant (lead-free 'N' suffix) | β |
| Process Technology | 0.30 Β΅m CMOS EEPROM | β |
| Security Bit | Programmable (one per device) | β |
| Macro Cells | β | 128 |
| Logic Array Blocks (LABs) | β | 8 (16 macro cells each) |
| User I/O Pins | β | 84 |
| Propagation Delay (tPD) | β | 10 ns |
| Maximum Frequency | β | 100 MHz |
| Supply Voltage (VCCINT) | β | 5 V (4.75 V to 5.25 V) |
| I/O Voltage Tolerance | β | 3.3 V or 5 V (MultiVolt interface) |
| Configuration Memory | β | EEPROM (non-volatile) |
| Programming Interface | β | JTAG (IEEE Std 1149.1), 4-pin |
| Mounting Type | β | Surface Mount |
| Lead-Free / RoHS Status | β | Lead-free (N suffix) |
| Architecture Generation | β | Second-generation MAX |