EPM7128SQC100-7N vs EPM7128STC100-15N Comparison
Detailed side-by-side comparison of EPM7128SQC100-7N by Intel and EPM7128STC100-15N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128SQC100-7N
EPM7128SQC100-7N - MAX 7000 CPLD, 128 Macrocells, 7.5ns, 100-Pin PQFP | Intel (Altera)
EPM7128SQC100-7N ObsoleteIntel
EPM7128STC100-15N
EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
EPM7128STC100-15N ObsoleteSpecification Comparison
| Parameter | EPM7128SQC100-7N | EPM7128STC100-15N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.10 | $9.20 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD - Complex Programmable Logic Device | β |
| Program Memory Type | EEPROM | β |
| Number of Macrocells | 128 | β |
| Number of Logic Array Blocks | 8 | β |
| Number of Global Clocks | 2 | β |
| Product Terms per Macrocell | 32 | β |
| Usable Gates | 2,500 | 2,500 |
| System Gates | 5,000 (max) | β |
| Maximum User I/Os | 84 | β |
| Pin-to-Pin Delay (tPD) | 7.5 ns | β |
| Counter Speed | 175.4 MHz | β |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | β |
| Operating Voltage (Core) | 5.0 V | β |
| I/O Standard Support | multiVolt (2.5V, 3.3V, 5.0V) | β |
| Package | 100-pin PQFP (QFP-100) | 100-pin TQFP |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| RoHS Status | Compliant (lead-free 'N' suffix) | Non-RoHS (legacy SnPb finish typical) |
| Process Technology | 0.30 Β΅m CMOS EEPROM | β |
| Security Bit | Programmable (one per device) | β |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Macro Cells | β | 128 |
| Logic Array Blocks (LABs) | β | 8 (16 macro cells each) |
| Maximum User I/O | β | 84 |
| Pin-to-Pin Logic Delay (tPD) | β | 15 ns (-15 speed grade) |
| Maximum Internal Frequency | β | 76.9 MHz |
| Supply Voltage (VCC) | β | 5 V (4.75 V to 5.25 V) |
| Supply Voltage (VCCIO) | β | 3.3 V or 5 V (per bank) |
| Technology | β | CMOS EEPROM, in-system programmable |
| JTAG (IEEE 1149.1) | β | Yes - in-system programming |
| Output Options | β | Totem-pole or open-drain (per pin) |
| Dedicated Inputs | β | 4 global inputs |
| Lifecycle Status | β | Obsolete (PDN effective 2017-06-01) |