EPM7128SQC160-6 vs EPM7128SQI160-10 Comparison
Detailed side-by-side comparison of EPM7128SQC160-6 by Altera and EPM7128SQI160-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128SQC160-6 - MAX 7000S 128-Macro Cell CPLD, 6ns, PQFP-160 | Altera/Intel
EPM7128SQC160-6 ObsoleteIntel
EPM7128SQI160-10 - 128-Macrocell MAX 7000S CPLD, 10ns, PQFP-160 | Intel
EPM7128SQI160-10 ObsoleteSpecification Comparison
| Parameter | EPM7128SQC160-6 | EPM7128SQI160-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $11.10 | $19.95 |
| Series | MAX 7000S | β |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Macro Cells | 128 | β |
| Usable Gates | 2500 | β |
| User I/O Pins | 100 | 100 (approx., PQFP-160) |
| Logic Array Blocks (LABs) | 4 | β |
| Pin-to-Pin Propagation Delay (tPD) | 6 ns | β |
| Maximum Internal Frequency (fMAX) | 147.1 MHz | β |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V nominal) | β |
| Process Technology | 0.5 Β΅m CMOS EEPROM | CMOS, EEPROM-based configuration |
| Programmable Type | In-System Programmable (ISP) via JTAG | β |
| Operating Temperature (Commercial) | 0 Β°C to +70 Β°C | β |
| Package | 160-Pin PQFP (28 Γ 28 mm) | PQFP-160 (Plastic Quad Flat Pack) |
| Mounting Type | Surface Mount | Surface Mount |
| Supplier Device Package | 160-PQFP (28Γ28) | β |
| JTAG Support | Yes (IEEE Std 1149.1) | β |
| RoHS Status | [DATA_NEEDED: RoHS status β Altera MAX 7000S family was originally lead-based; lead-free variants exist with -N suffix] | [DATA_NEEDED: rohs_status] |
| MSL Level | [DATA_NEEDED: MSL rating not in verified data] | β |
| Family | β | MAX 7000S |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocells | β | 128 |
| Logic Elements / Gates | β | 2.5K equivalent gates |
| Propagation Delay (tPD) | β | 10 ns |
| Maximum Frequency | β | 100 MHz |
| Logic Blocks (LABs) | β | 4 (16 macrocells each) |
| Supply Voltage VCCINT | β | 5 V |
| I/O Voltage Tolerance | β | 3.3 V / 5 V multi-volt interface |
| Programming Interface | β | JTAG (IEEE 1149.1) / ISP |
| Operating Temperature Grade | β | Industrial (-40C to +85C) |
| Configuration Memory | β | EEPROM (non-volatile, instant-on) |