EPM7128STC100-10 vs EPM7128SQC100-10N Comparison

Detailed side-by-side comparison of EPM7128STC100-10 by Altera and EPM7128SQC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM7128STC100-10

EPM7128STC100-10 - 128-Macro MAX 7000S CPLD, 10ns TQFP-100 | Intel / Altera

EPM7128STC100-10 Obsolete
Altera
EPM7128SQC100-10N

EPM7128SQC100-10N - MAX 7000 128-Macro-Cell CPLD, 10ns | Altera

EPM7128SQC100-10N βœ“ Active

Specification Comparison

Parameter EPM7128STC100-10 EPM7128SQC100-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Active
Stock Status In Stock In Stock
Unit Price (USD) $7.10 $14.95
Family MAX 7000S MAX 7000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 128 128
Usable Gates 2,500 2,500
User I/Os 84 β€”
Logic Array Blocks 8 (16 macrocells per LAB) β€”
Propagation Delay (tPD) 10 ns 10 ns
Internal Counter Frequency (fCNT) 100 MHz β€”
Logic Family CMOS β€”
Supply Voltage (VCCINT) 5 V 5 V (4.75 V to 5.25 V)
MultiVolt I/O Voltage 3.3 V / 5 V β€”
Package TQFP-100 (C100) 100-pin PQFP (BQFP)
Pin Count 100 β€”
Mounting Type Surface Mount Surface Mount
Programmability In-System Programmable (JTAG, IEEE 1149.1), EEPROM β€”
Operating Temperature 0C to +70C (commercial) -40C to +85C (industrial)
RoHS Status [DATA_NEEDED: RoHS compliance status not in provided data] β€”
Logic Array Blocks (LABs) β€” 8 (16 macro cells each)
User I/O Pins β€” 84
Maximum Frequency β€” 100 MHz
I/O Voltage Tolerance β€” 3.3 V or 5 V (MultiVolt interface)
Configuration Memory β€” EEPROM (non-volatile)
Programming Interface β€” JTAG (IEEE Std 1149.1), 4-pin
Lead-Free / RoHS Status β€” Lead-free (N suffix)
Architecture Generation β€” Second-generation MAX

Datasheets & Resources

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