EPM7128STC100-15N vs EPM7128STC100-6N Comparison
Detailed side-by-side comparison of EPM7128STC100-15N by Intel and EPM7128STC100-6N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128STC100-15N
EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
EPM7128STC100-15N ObsoleteAltera
EPM7128STC100-6N
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N ObsoleteSpecification Comparison
| Parameter | EPM7128STC100-15N | EPM7128STC100-6N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.20 | $10.50 |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Family | MAX 7000S | MAX 7000S |
| Usable Gates | 2,500 | 2,500 |
| Macro Cells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | β |
| Maximum User I/O | 84 | β |
| Pin-to-Pin Logic Delay (tPD) | 15 ns (-15 speed grade) | β |
| Maximum Internal Frequency | 76.9 MHz | 147.1 MHz |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | β |
| Supply Voltage (VCCIO) | 3.3 V or 5 V (per bank) | 5 V |
| Technology | CMOS EEPROM, in-system programmable | β |
| Package | 100-pin TQFP | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| JTAG (IEEE 1149.1) | Yes - in-system programming | β |
| Output Options | Totem-pole or open-drain (per pin) | β |
| Dedicated Inputs | 4 global inputs | β |
| RoHS Status | Non-RoHS (legacy SnPb finish typical) | Non-Compliant (lead-bearing package) |
| Lifecycle Status | Obsolete (PDN effective 2017-06-01) | β |
| User I/Os | β | 84 |
| Logic Family | β | CMOS |
| Number of Pins | β | 100 |
| Package Type | β | TQFP-100 |
| Internal Counter Frequency | β | 250 MHz |
| Propagation Delay (tPD) | β | 6 ns |
| Pin-to-Pin Delay | β | 4.5 ns |
| Process Technology | β | CMOS EEPROM |
| Programmability | β | In-System Programmable (ISP) via JTAG |
| JTAG Support | β | IEEE 1149.1 Boundary Scan |
| Mounting Type | β | Surface Mount |