EPM7128STC100-6N vs EPM7128SQC100-10N Comparison
Detailed side-by-side comparison of EPM7128STC100-6N by Altera and EPM7128SQC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N Obsolete
Specification Comparison
| Parameter | EPM7128STC100-6N | EPM7128SQC100-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.50 | $14.95 |
| Family | MAX 7000S | MAX 7000 |
| Usable Gates | 2,500 | 2,500 |
| Macro Cells | 128 | 128 |
| User I/Os | 84 | β |
| Logic Family | CMOS | β |
| Number of Pins | 100 | β |
| Package Type | TQFP-100 | β |
| Maximum Internal Frequency | 147.1 MHz | β |
| Internal Counter Frequency | 250 MHz | β |
| Propagation Delay (tPD) | 6 ns | 10 ns |
| Pin-to-Pin Delay | 4.5 ns | β |
| Supply Voltage (VCCIO) | 5 V | β |
| Process Technology | CMOS EEPROM | β |
| Programmability | In-System Programmable (ISP) via JTAG | β |
| JTAG Support | IEEE 1149.1 Boundary Scan | β |
| Operating Temperature | 0C to +70C (Commercial) | -40C to +85C (industrial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Non-Compliant (lead-bearing package) | β |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | β | 8 (16 macro cells each) |
| User I/O Pins | β | 84 |
| Maximum Frequency | β | 100 MHz |
| Supply Voltage (VCCINT) | β | 5 V (4.75 V to 5.25 V) |
| I/O Voltage Tolerance | β | 3.3 V or 5 V (MultiVolt interface) |
| Package | β | 100-pin PQFP (BQFP) |
| Configuration Memory | β | EEPROM (non-volatile) |
| Programming Interface | β | JTAG (IEEE Std 1149.1), 4-pin |
| Lead-Free / RoHS Status | β | Lead-free (N suffix) |
| Architecture Generation | β | Second-generation MAX |