EPM7128STC100-6N vs EPM7128STC100-15N Comparison
Detailed side-by-side comparison of EPM7128STC100-6N by Altera and EPM7128STC100-15N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N ObsoleteIntel
EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
EPM7128STC100-15N ObsoleteSpecification Comparison
| Parameter | EPM7128STC100-6N | EPM7128STC100-15N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.50 | $9.20 |
| Family | MAX 7000S | MAX 7000S |
| Usable Gates | 2,500 | 2,500 |
| Macro Cells | 128 | 128 |
| User I/Os | 84 | β |
| Logic Family | CMOS | β |
| Number of Pins | 100 | β |
| Package Type | TQFP-100 | β |
| Maximum Internal Frequency | 147.1 MHz | 76.9 MHz |
| Internal Counter Frequency | 250 MHz | β |
| Propagation Delay (tPD) | 6 ns | β |
| Pin-to-Pin Delay | 4.5 ns | β |
| Supply Voltage (VCCIO) | 5 V | 3.3 V or 5 V (per bank) |
| Process Technology | CMOS EEPROM | β |
| Programmability | In-System Programmable (ISP) via JTAG | β |
| JTAG Support | IEEE 1149.1 Boundary Scan | β |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Mounting Type | Surface Mount | β |
| RoHS Status | Non-Compliant (lead-bearing package) | Non-RoHS (legacy SnPb finish typical) |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | β | 8 (16 macro cells each) |
| Maximum User I/O | β | 84 |
| Pin-to-Pin Logic Delay (tPD) | β | 15 ns (-15 speed grade) |
| Supply Voltage (VCC) | β | 5 V (4.75 V to 5.25 V) |
| Technology | β | CMOS EEPROM, in-system programmable |
| Package | β | 100-pin TQFP |
| JTAG (IEEE 1149.1) | β | Yes - in-system programming |
| Output Options | β | Totem-pole or open-drain (per pin) |
| Dedicated Inputs | β | 4 global inputs |
| Lifecycle Status | β | Obsolete (PDN effective 2017-06-01) |