EPM7160SLC84-10N vs EPM7160STI100-10N Comparison
Detailed side-by-side comparison of EPM7160SLC84-10N by Intel and EPM7160STI100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7160SLC84-10N
EPM7160SLC84-10N - MAX 7000S CPLD 160 Macrocells 84-PLCC | Intel
EPM7160SLC84-10N ObsoleteAltera
EPM7160STI100-10N
EPM7160STI100-10N - MAX 7000S CPLD, 160 Macrocells, 100MHz, TQFP-100 | Intel/Altera
EPM7160STI100-10N β Last Time BuySpecification Comparison
| Parameter | EPM7160SLC84-10N | EPM7160STI100-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.85 | $7.80 |
| Family | MAX 7000S | MAX 7000S |
| Logic Elements / Macrocells | 160 macrocells | β |
| Usable Gates | 3,200 gates | 3200 |
| Logic Array Blocks (LABs) | 4 | β |
| User I/O Pins | 64 (also reported as 60 or 36 depending on variant) | β |
| Pin-to-Pin Delay (tPD) | 10 ns | β |
| Counter Speed (fCNT) | up to 175.4 MHz | β |
| Maximum Operating Frequency | 100 MHz | β |
| Supply Voltage - Core (VCC) | 5.0 V | β |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5.0 V | β |
| Configuration Memory | EEPROM (non-volatile) | β |
| In-System Programming | Yes, via IEEE Std. 1149.1 JTAG | β |
| Program / Erase Cycles | 100 minimum | β |
| Data Retention | 20 years minimum | β |
| Package | 84-pin PLCC (J-lead, surface mount) | β |
| Operating Temperature Grade | Commercial (0C to +70C) | β |
| Lead-Free / RoHS | Yes (-N suffix indicates lead-free) | Yes (lead-free per 'I' industrial suffix) |
| Mounting Type | Surface Mount | Surface Mount |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocells | β | 160 |
| User I/Os | β | 84 (per Mouser listing; up to 104 per alternate datasheets) |
| Logic Blocks | β | 10 (LABs) |
| Propagation Delay (tPD) | β | 10 ns |
| Internal Frequency | β | 100 MHz |
| Supply Voltage VCC | β | 5.0 V (3.3 V or 5 V tolerant I/O via MAX 7000S multi-voltage ISP) |
| Programmable Technology | β | EEPROM (non-volatile) |
| In-System Programmability | β | Yes (JTAG/IEEE 1149.1, 5.0V ISP) |
| Operating Temperature | β | -40C to +85C (industrial, 'I' suffix) |
| Package Type | β | 100-pin TQFP (TQFP-100) |
| Process Technology | β | CMOS, EEPROM-based |