EPM7160SLC84-6 vs EPM7160SLC84-10 Comparison
Detailed side-by-side comparison of EPM7160SLC84-6 by Intel and EPM7160SLC84-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7160SLC84-6
EPM7160SLC84-6 - MAX 7000S CPLD 160 Macro 6ns 84-PLCC | Intel
EPM7160SLC84-6 ObsoleteAltera
EPM7160SLC84-10
EPM7160SLC84-10 - 160-Macrocell MAX 7000S CPLD | Altera
EPM7160SLC84-10 ObsoleteSpecification Comparison
| Parameter | EPM7160SLC84-6 | EPM7160SLC84-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.86 | $35.77 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | EE PLD (CPLD) | β |
| Macrocells | 160 | 160 |
| Logic Array Blocks (LABs) | 4 (16 macrocells each) | 4 |
| Usable Gates | 3.2K | 3,200 |
| User I/O Pins | 36 (also reported as 64 depending on source) | β |
| Pin-to-Pin Delay (tPD) | 6 ns (speed grade -6) | β |
| Counter Frequency (fCNT) | 149.3 MHz | β |
| Supply Voltage | 4.75 V to 5.25 V (single 5 V supply) | β |
| Process Technology | CMOS EEPROM | β |
| In-System Programmability | Yes (5.0 V ISP via JTAG) | Yes (IEEE 1149.1 JTAG, 5.0 V) |
| JTAG Support | IEEE Std. 1149.1 compliant | β |
| MultiVolt I/O | Yes (mixed-voltage interface) | β |
| Package | 84-pin PLCC (29.31 x 29.31 mm) | 84-Pin PLCC (J-Lead) |
| Mounting Type | Surface Mount (J-Lead) | Surface Mount |
| Operating Temperature | [DATA_NEEDED: commercial vs industrial grade] | 0C to +70C (Commercial) |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS status] |
| Maximum User I/O Pins | β | 64 |
| Propagation Delay (tPD) | β | 10 ns |
| Maximum Operating Frequency | β | 100 MHz |
| Supply Voltage (VCCINT/VCCIO) | β | 5.0 V |
| Technology | β | EEPROM-based CMOS |
| JTAG Boundary Scan | β | Yes (IEEE Std. 1149.1 compliant) |