EPM7160SLC84-6 vs EPM7160SLC84-15 Comparison

Detailed side-by-side comparison of EPM7160SLC84-6 by Intel and EPM7160SLC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7160SLC84-6 EPM7160SLC84-15
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $15.86 $10.80
Family MAX 7000S MAX 7000
Device Type EE PLD (CPLD) β€”
Macrocells 160 160
Logic Array Blocks (LABs) 4 (16 macrocells each) β€”
Usable Gates 3.2K 3,200
User I/O Pins 36 (also reported as 64 depending on source) β€”
Pin-to-Pin Delay (tPD) 6 ns (speed grade -6) β€”
Counter Frequency (fCNT) 149.3 MHz β€”
Supply Voltage 4.75 V to 5.25 V (single 5 V supply) β€”
Process Technology CMOS EEPROM β€”
In-System Programmability Yes (5.0 V ISP via JTAG) β€”
JTAG Support IEEE Std. 1149.1 compliant β€”
MultiVolt I/O Yes (mixed-voltage interface) β€”
Package 84-pin PLCC (29.31 x 29.31 mm) β€”
Mounting Type Surface Mount (J-Lead) Surface Mount (PLCC socket or direct solder)
Operating Temperature [DATA_NEEDED: commercial vs industrial grade] 0 C to 70 C
RoHS Status Compliant Not RoHS compliant (contains lead, SnPb finish typical)
Maximum Propagation Delay β€” 15 ns
Maximum User I/O Pins β€” 64
Supply Voltage (VCCINT/VCIO) β€” 4.75 V to 5.25 V (5 V nominal)
I/O Logic Level β€” Configurable 3.3 V or 5 V
Technology β€” CMOS, EEPROM configuration
Package Type β€” PLCC-84 (PQCC84, JEDEC S-PQCC-J84)
Terminal Pitch β€” 1.270 mm
Programming Interface β€” JTAG (IEEE 1149.1) in-system programmable
Lifecycle β€” Obsolete / last-time-buy (per Altera/Intel PDN)

Datasheets & Resources

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