EPM7160SQC160-10 vs EPM7160SQC160-6 Comparison
Detailed side-by-side comparison of EPM7160SQC160-10 by Altera and EPM7160SQC160-6 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7160SQC160-10
EPM7160SQC160-10 - MAX 7000S CPLD, 160 Macro Cells, 100MHz, PQFP-160 | Intel / Altera
EPM7160SQC160-10 ObsoleteAltera
EPM7160SQC160-6
EPM7160SQC160-6 - 160-Macrocell MAX 7000S CPLD, 6ns, PQFP-160 | Altera
EPM7160SQC160-6 ObsoleteSpecification Comparison
| Parameter | EPM7160SQC160-10 | EPM7160SQC160-6 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $12.20 | $5.45 |
| Family | MAX 7000S | β |
| Macro Cells | 160 | β |
| Logic Elements / Gates | 3,200 usable gates | β |
| User I/Os | 104 | β |
| Logic Array Blocks (LABs) | 10 | β |
| Maximum Operating Frequency | 100 MHz | β |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | β |
| Supply Voltage (VCCINT) | 5.0 V | 4.75 V to 5.25 V (nominal 5 V) |
| I/O Voltage Tolerance | 5.0 V | β |
| Programming Technology | EEPROM, in-system programmable | β |
| JTAG Support | IEEE 1149.1 (boundary-scan + ISP) | β |
| Package | PQFP-160 (SQC160) | 160-pin PQFP (Plastic Quad Flat Pack), 28x28 mm body |
| Operating Temperature | 0 C to +70 C (commercial) | 0 C to 70 C (commercial) |
| Logic Family | CMOS | CMOS, TTL-compatible I/O |
| Mounting Type | Surface Mount | Surface Mount |
| Process Technology | CMOS, EEPROM-based | β |
| RoHS Status | unknown | β |
| Lead-Free | unknown | β |
| Series | β | MAX 7000S |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Programmable Type | β | In System Programmable (ISP), EEPROM-based |
| Number of Macrocells | β | 160 |
| Number of Logic Elements/Blocks | β | 10 LABs (Logic Array Blocks) |
| Number of Usable Gates | β | 3,200 |
| Number of I/O Pins | β | 104 |
| Propagation Delay (tpd) | β | 6 ns (max, pin-to-pin) |
| Maximum Internal Frequency | β | 167 MHz |
| Program/Erase Endurance | β | 100 cycles (EEPROM) |
| JTAG / Boundary Scan | β | IEEE Std 1149.1 compliant |
| Dedicated Input Pins | β | 4 (GCLK1, GCLRn, OE1, OE2/GCLK2) |