EPM7160SQC160-10N vs EPM7160SQC160-7 Comparison

Detailed side-by-side comparison of EPM7160SQC160-10N by Intel and EPM7160SQC160-7 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPM7160SQC160-10N

EPM7160SQC160-10N - 160 Macrocells MAX 7000S CPLD, 10ns, PQFP-160

EPM7160SQC160-10N Nrnd
Altera
EPM7160SQC160-7

EPM7160SQC160-7 - 160-Macrocell MAX 7000S CPLD, 7.5ns | Altera

EPM7160SQC160-7 Obsolete

Specification Comparison

Parameter EPM7160SQC160-10N EPM7160SQC160-7
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.10 $9.75
Family MAX 7000S MAX 7000S
Macro Cells 160 β€”
Usable Gates 3,200 β€”
Logic Elements / Blocks 10 Logic Array Blocks (LABs) β€”
User I/O Pins 104 β€”
Pin-to-Pin Delay (tPD) 10 ns β€”
Maximum Internal Frequency 167 MHz β€”
Counter Speed (fCNT) 100 MHz β€”
Supply Voltage (VCCINT) 5.0 V 4.75 V to 5.25 V (5.0 V nominal)
In-System Programmability Yes (JTAG IEEE 1149.1) β€”
Operating Temperature 0 C to 70 C (Commercial) 0 Β°C to 70 Β°C (commercial)
Package PQFP-160 (SQC) 31.2 x 31.2 mm 160-pin PQFP (BQFP, 28x28 mm)
Mounting Type Surface Mount Surface Mount
RoHS Status Non-Compliant (Pb-bearing PQFP) Not Compliant (per Arrow listing)
Memory Technology EEPROM β€”
Macrocells β€” 160
Logic Array Blocks (LABs) β€” 10
Usable System Gates β€” 3,200
Product Terms per Macrocell β€” 32
Maximum User I/Os β€” 104
Global Clocks β€” 2
Speed Grade β€” -7 (7.5 ns pin-to-pin)
Maximum Propagation Delay (tPD) β€” 7.5 ns
Program Memory Type β€” EEPROM (in-system programmable)
JTAG (IEEE 1149.1) β€” Yes (ISP via JTAG)
PCI Compliance β€” PCI Local Bus Specification Revision 2.2
Part Status β€” Obsolete

Datasheets & Resources

Browse All Products Create BOM Request Quote