EPM7160SQC160-7 vs EPM7160SQC160-10N Comparison
Detailed side-by-side comparison of EPM7160SQC160-7 by Altera and EPM7160SQC160-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7160SQC160-7 | EPM7160SQC160-10N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $8.10 |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 160 | β |
| Logic Array Blocks (LABs) | 10 | β |
| Usable System Gates | 3,200 | β |
| Product Terms per Macrocell | 32 | β |
| Maximum User I/Os | 104 | β |
| Global Clocks | 2 | β |
| Speed Grade | -7 (7.5 ns pin-to-pin) | β |
| Maximum Propagation Delay (tPD) | 7.5 ns | β |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | 5.0 V |
| Program Memory Type | EEPROM (in-system programmable) | β |
| Operating Temperature | 0 Β°C to 70 Β°C (commercial) | 0 C to 70 C (Commercial) |
| Package | 160-pin PQFP (BQFP, 28x28 mm) | PQFP-160 (SQC) 31.2 x 31.2 mm |
| Mounting Type | Surface Mount | Surface Mount |
| JTAG (IEEE 1149.1) | Yes (ISP via JTAG) | β |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | β |
| RoHS Status | Not Compliant (per Arrow listing) | Non-Compliant (Pb-bearing PQFP) |
| Part Status | Obsolete | β |
| Macro Cells | β | 160 |
| Usable Gates | β | 3,200 |
| Logic Elements / Blocks | β | 10 Logic Array Blocks (LABs) |
| User I/O Pins | β | 104 |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Maximum Internal Frequency | β | 167 MHz |
| Counter Speed (fCNT) | β | 100 MHz |
| In-System Programmability | β | Yes (JTAG IEEE 1149.1) |
| Memory Technology | β | EEPROM |