EPM7192EGI160-20 vs EPM7192EQC160-20 Comparison
Detailed side-by-side comparison of EPM7192EGI160-20 by Intel and EPM7192EQC160-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7192EGI160-20
EPM7192EGI160-20 - 192-Macrocell CPLD, 20ns, 160-PGA | Intel
EPM7192EGI160-20 NrndIntel
EPM7192EQC160-20
EPM7192EQC160-20 - 192-Macrocell MAX 7000 CPLD, 20ns, PQFP-160 | Intel
EPM7192EQC160-20 ObsoleteSpecification Comparison
| Parameter | EPM7192EGI160-20 | EPM7192EQC160-20 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $264.10 | $58.26 |
| Family | MAX 7000 | β |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 192 | β |
| Logic Array Blocks | 4 | β |
| User I/O Pins | 36 | β |
| Dedicated Inputs | 4 | β |
| Pin-to-Pin Delay (tpd) | 20 ns | β |
| Maximum Operating Frequency | 62.5 MHz | β |
| Supply Voltage (VCCINT) | 5.0 V | 4.75 V to 5.25 V |
| Program Memory Type | EEPROM | β |
| In-System Programmability | Yes (JTAG IEEE Std. 1149.1) | β |
| Package | 160-pin CPGA (Ceramic Pin Grid Array) | β |
| Operating Temperature Grade | Industrial (-40C to +85C) | β |
| RoHS Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status - non-RoHS era part] |
| Programming Interface | JTAG (ByteBlaster / USB-Blaster compatible) | β |
| Series | β | MAX 7000 |
| Programmable Type | β | EE PLD (EEPROM-based) |
| Number of Macrocells | β | 192 |
| Number of Logic Array Blocks | β | 4 |
| Number of User I/O Pins | β | 124 (per package), 36 (per data source variant description) |
| Delay Time (tPD) | β | 20 ns |
| Internal Counter Frequency (fCNT) | β | 100 MHz typical |
| Operating Temperature | β | -40C to +85C (industrial) |
| Package / Case | β | 160-BQFP / 160-PQFP (28x28 mm) |
| Mounting Type | β | Surface Mount |
| In-System Programmable (ISP) | β | Yes, 5.0 V ISP via JTAG (IEEE Std. 1149.1) |
| Programmable Security Bit | β | Yes |
| Power-Saving Mode | β | Yes, programmable per macrocell |
| MSL Level | β | [DATA_NEEDED: MSL rating] |