EPM7192EGM160-15 vs EPM7192EGM160-20 Comparison
Detailed side-by-side comparison of EPM7192EGM160-15 by Altera and EPM7192EGM160-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7192EGM160-15
EPM7192EGM160-15 - MAX 7000 CPLD, 192 Macrocells, PGA-160 | Altera
EPM7192EGM160-15 NrndAltera
EPM7192EGM160-20
EPM7192EGM160-20 - 192-Macrocell MAX 7000 CPLD, 20ns PGA-160 | Altera
EPM7192EGM160-20 ObsoleteSpecification Comparison
| Parameter | EPM7192EGM160-15 | EPM7192EGM160-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $36.80 | $15.60 |
| Family | MAX 7000 | MAX 7000 |
| Sub-family | MAX 7000E | β |
| Device | EPM7192E | β |
| Macrocells | 192 | 192 |
| Usable Gates | 3750 | 600 to 5,000 |
| Logic Array Blocks (LABs) | 12 (16 macrocells each) | 12 |
| User I/O Pins | 124 | β |
| Package | 160-pin PGA (Pin Grid Array), ceramic | PGA-160 (160-pin Pin Grid Array) |
| Pin-to-Pin Logic Delay (tPD) | 15 ns | β |
| Supply Voltage (Core) | 5 V Β±5% | β |
| I/O Voltage | 3.3 V or 5 V configurable | β |
| Technology | CMOS EEPROM (0.5 Β΅m) | β |
| Programming Interface | JTAG (ByteBlaster / BitBlaster) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | -40C to +125C (industrial) |
| Mounting Type | Through-hole (PGA socket) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Device Type | β | EE CMOS CPLD (Electrically Erasable) |
| Maximum User I/O Pins | β | 120 |
| Speed Grade | β | -20 (20 ns pin-to-pin) |
| Pin-to-Pin Propagation Delay | β | 20 ns |
| Counter Frequency (max) | β | 175.4 MHz |
| I/O Standards | β | 3.3 V or 5 V configurable |
| Global Clock Inputs | β | 2 (GCLK1, GCLK2) |
| In-System Programming | β | Yes (JTAG IEEE 1149.1) |
| Program/Erase Endurance | β | 100 cycles (EEPROM) |
| Technology Node | β | CMOS, second-generation MAX architecture |