EPM7192EGM160-15 vs EPM7192EQC160-20 Comparison
Detailed side-by-side comparison of EPM7192EGM160-15 by Altera and EPM7192EQC160-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7192EGM160-15
EPM7192EGM160-15 - MAX 7000 CPLD, 192 Macrocells, PGA-160 | Altera
EPM7192EGM160-15 NrndIntel
EPM7192EQC160-20
EPM7192EQC160-20 - 192-Macrocell MAX 7000 CPLD, 20ns, PQFP-160 | Intel
EPM7192EQC160-20 ObsoleteSpecification Comparison
| Parameter | EPM7192EGM160-15 | EPM7192EQC160-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $36.80 | $58.26 |
| Family | MAX 7000 | β |
| Sub-family | MAX 7000E | β |
| Device | EPM7192E | β |
| Macrocells | 192 | β |
| Usable Gates | 3750 | β |
| Logic Array Blocks (LABs) | 12 (16 macrocells each) | β |
| User I/O Pins | 124 | β |
| Package | 160-pin PGA (Pin Grid Array), ceramic | β |
| Pin-to-Pin Logic Delay (tPD) | 15 ns | β |
| Supply Voltage (Core) | 5 V Β±5% | β |
| I/O Voltage | 3.3 V or 5 V configurable | β |
| Technology | CMOS EEPROM (0.5 Β΅m) | β |
| Programming Interface | JTAG (ByteBlaster / BitBlaster) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| Mounting Type | Through-hole (PGA socket) | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - non-RoHS era part] |
| Series | β | MAX 7000 |
| Programmable Type | β | EE PLD (EEPROM-based) |
| Number of Macrocells | β | 192 |
| Number of Logic Array Blocks | β | 4 |
| Number of User I/O Pins | β | 124 (per package), 36 (per data source variant description) |
| Delay Time (tPD) | β | 20 ns |
| Internal Counter Frequency (fCNT) | β | 100 MHz typical |
| Supply Voltage (VCCINT) | β | 4.75 V to 5.25 V |
| Package / Case | β | 160-BQFP / 160-PQFP (28x28 mm) |
| In-System Programmable (ISP) | β | Yes, 5.0 V ISP via JTAG (IEEE Std. 1149.1) |
| Programmable Security Bit | β | Yes |
| Power-Saving Mode | β | Yes, programmable per macrocell |
| MSL Level | β | [DATA_NEEDED: MSL rating] |