EPM7192EGM160-20 vs EPM7192EGI160-20 Comparison
Detailed side-by-side comparison of EPM7192EGM160-20 by Altera and EPM7192EGI160-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7192EGM160-20 - 192-Macrocell MAX 7000 CPLD, 20ns PGA-160 | Altera
EPM7192EGM160-20 ObsoleteSpecification Comparison
| Parameter | EPM7192EGM160-20 | EPM7192EGI160-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.60 | $264.10 |
| Family | MAX 7000 | MAX 7000 |
| Device Type | EE CMOS CPLD (Electrically Erasable) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | β |
| Usable Gates | 600 to 5,000 | β |
| Maximum User I/O Pins | 120 | β |
| Package | PGA-160 (160-pin Pin Grid Array) | 160-pin CPGA (Ceramic Pin Grid Array) |
| Speed Grade | -20 (20 ns pin-to-pin) | β |
| Pin-to-Pin Propagation Delay | 20 ns | β |
| Counter Frequency (max) | 175.4 MHz | β |
| I/O Standards | 3.3 V or 5 V configurable | β |
| Global Clock Inputs | 2 (GCLK1, GCLK2) | β |
| In-System Programming | Yes (JTAG IEEE 1149.1) | β |
| Program/Erase Endurance | 100 cycles (EEPROM) | β |
| Operating Temperature | -40C to +125C (industrial) | β |
| Technology Node | CMOS, second-generation MAX architecture | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status] |
| Logic Array Blocks | β | 4 |
| User I/O Pins | β | 36 |
| Dedicated Inputs | β | 4 |
| Pin-to-Pin Delay (tpd) | β | 20 ns |
| Maximum Operating Frequency | β | 62.5 MHz |
| Supply Voltage (VCCINT) | β | 5.0 V |
| Program Memory Type | β | EEPROM |
| In-System Programmability | β | Yes (JTAG IEEE Std. 1149.1) |
| Operating Temperature Grade | β | Industrial (-40C to +85C) |
| Programming Interface | β | JTAG (ByteBlaster / USB-Blaster compatible) |