EPM7192EGM160-20 vs EPM7192EGM160-15 Comparison
Detailed side-by-side comparison of EPM7192EGM160-20 by Altera and EPM7192EGM160-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7192EGM160-20 - 192-Macrocell MAX 7000 CPLD, 20ns PGA-160 | Altera
EPM7192EGM160-20 ObsoleteSpecification Comparison
| Parameter | EPM7192EGM160-20 | EPM7192EGM160-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.60 | $36.80 |
| Family | MAX 7000 | MAX 7000 |
| Device Type | EE CMOS CPLD (Electrically Erasable) | β |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 (16 macrocells each) |
| Usable Gates | 600 to 5,000 | 3750 |
| Maximum User I/O Pins | 120 | β |
| Package | PGA-160 (160-pin Pin Grid Array) | 160-pin PGA (Pin Grid Array), ceramic |
| Speed Grade | -20 (20 ns pin-to-pin) | β |
| Pin-to-Pin Propagation Delay | 20 ns | β |
| Counter Frequency (max) | 175.4 MHz | β |
| I/O Standards | 3.3 V or 5 V configurable | β |
| Global Clock Inputs | 2 (GCLK1, GCLK2) | β |
| In-System Programming | Yes (JTAG IEEE 1149.1) | β |
| Program/Erase Endurance | 100 cycles (EEPROM) | β |
| Operating Temperature | -40C to +125C (industrial) | [DATA_NEEDED: operating temperature range] |
| Technology Node | CMOS, second-generation MAX architecture | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Sub-family | β | MAX 7000E |
| Device | β | EPM7192E |
| User I/O Pins | β | 124 |
| Pin-to-Pin Logic Delay (tPD) | β | 15 ns |
| Supply Voltage (Core) | β | 5 V Β±5% |
| I/O Voltage | β | 3.3 V or 5 V configurable |
| Technology | β | CMOS EEPROM (0.5 Β΅m) |
| Programming Interface | β | JTAG (ByteBlaster / BitBlaster) |
| Mounting Type | β | Through-hole (PGA socket) |