EPM7192SQC160-10 vs EPM7192EGM160-20 Comparison
Detailed side-by-side comparison of EPM7192SQC160-10 by Altera and EPM7192EGM160-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7192SQC160-10
EPM7192SQC160-10 - 192-Macro MAX 7000S CPLD, 100MHz, PQFP-160 | Intel / Altera
EPM7192SQC160-10 NrndAltera
EPM7192EGM160-20
EPM7192EGM160-20 - 192-Macrocell MAX 7000 CPLD, 20ns PGA-160 | Altera
EPM7192EGM160-20 ObsoleteSpecification Comparison
| Parameter | EPM7192SQC160-10 | EPM7192EGM160-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $18.25 | $15.60 |
| Family | MAX 7000S | MAX 7000 |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 4 | 12 |
| User I/Os | 124 | β |
| Usable Gates | 3750 | 600 to 5,000 |
| Propagation Delay (tPD) | 10 ns | β |
| Maximum Operating Frequency | 100 MHz | β |
| Supply Voltage (VCCINT) | 5.0 V | β |
| Program Memory Type | EEPROM | β |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | β |
| Package | PQFP-160 (SQC) 28x28 mm | PGA-160 (160-pin Pin Grid Array) |
| Pin/Package Type | Surface Mount, Gull-Wing | β |
| Operating Temperature (Commercial) | 0C to +70C | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead finish] | β |
| Device Type | β | EE CMOS CPLD (Electrically Erasable) |
| Maximum User I/O Pins | β | 120 |
| Speed Grade | β | -20 (20 ns pin-to-pin) |
| Pin-to-Pin Propagation Delay | β | 20 ns |
| Counter Frequency (max) | β | 175.4 MHz |
| I/O Standards | β | 3.3 V or 5 V configurable |
| Global Clock Inputs | β | 2 (GCLK1, GCLK2) |
| In-System Programming | β | Yes (JTAG IEEE 1149.1) |
| Program/Erase Endurance | β | 100 cycles (EEPROM) |
| Operating Temperature | β | -40C to +125C (industrial) |
| Technology Node | β | CMOS, second-generation MAX architecture |