EPM7192SQC160-10 vs EPM7192EQC160-20 Comparison
Detailed side-by-side comparison of EPM7192SQC160-10 by Altera and EPM7192EQC160-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7192SQC160-10
EPM7192SQC160-10 - 192-Macro MAX 7000S CPLD, 100MHz, PQFP-160 | Intel / Altera
EPM7192SQC160-10 NrndIntel
EPM7192EQC160-20
EPM7192EQC160-20 - 192-Macrocell MAX 7000 CPLD, 20ns, PQFP-160 | Intel
EPM7192EQC160-20 ObsoleteSpecification Comparison
| Parameter | EPM7192SQC160-10 | EPM7192EQC160-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $18.25 | $58.26 |
| Family | MAX 7000S | β |
| Macrocells | 192 | β |
| Logic Array Blocks (LABs) | 4 | β |
| User I/Os | 124 | β |
| Usable Gates | 3750 | β |
| Propagation Delay (tPD) | 10 ns | β |
| Maximum Operating Frequency | 100 MHz | β |
| Supply Voltage (VCCINT) | 5.0 V | 4.75 V to 5.25 V |
| Program Memory Type | EEPROM | β |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | β |
| Package | PQFP-160 (SQC) 28x28 mm | β |
| Pin/Package Type | Surface Mount, Gull-Wing | β |
| Operating Temperature (Commercial) | 0C to +70C | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - non-RoHS era part] |
| Lead Finish | [DATA_NEEDED: lead finish] | β |
| Series | β | MAX 7000 |
| Programmable Type | β | EE PLD (EEPROM-based) |
| Number of Macrocells | β | 192 |
| Number of Logic Array Blocks | β | 4 |
| Number of User I/O Pins | β | 124 (per package), 36 (per data source variant description) |
| Delay Time (tPD) | β | 20 ns |
| Internal Counter Frequency (fCNT) | β | 100 MHz typical |
| Operating Temperature | β | -40C to +85C (industrial) |
| Package / Case | β | 160-BQFP / 160-PQFP (28x28 mm) |
| Mounting Type | β | Surface Mount |
| In-System Programmable (ISP) | β | Yes, 5.0 V ISP via JTAG (IEEE Std. 1149.1) |
| Programmable Security Bit | β | Yes |
| Power-Saving Mode | β | Yes, programmable per macrocell |
| MSL Level | β | [DATA_NEEDED: MSL rating] |