EPM7192SQI160-10 vs EPM7192SQI160-10N Comparison
Detailed side-by-side comparison of EPM7192SQI160-10 by Altera and EPM7192SQI160-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7192SQI160-10
EPM7192SQI160-10 - MAX 7000S CPLD 192 Macrocell | Altera
EPM7192SQI160-10 ObsoleteIntel
EPM7192SQI160-10N
EPM7192SQI160-10N - MAX 7000S CPLD, 192 Macrocells, 100MHz | Altera
EPM7192SQI160-10N NrndSpecification Comparison
| Parameter | EPM7192SQI160-10 | EPM7192SQI160-10N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $35.90 |
| Device Type | Complex Programmable Logic Device (CPLD) | β |
| Logic Family | MAX 7000S (EEPROM-based) | CMOS |
| Macrocells | 192 | β |
| User I/O Pins | 124 | β |
| Package | 160-pin Plastic QFP (QFP-160) | PQFP-160 (QFP-160, plastic) |
| Pin Count | 160 | 160 |
| Propagation Delay (tPD) | 7.5 ns | β |
| Internal Frequency | 167 MHz | β |
| Supply Voltage | 5.0 V | β |
| Programmability | In-System Programmable (ISP), EEPROM | β |
| Operating Temperature | 0 C to +70 C | 0C to +70C (industrial, 'N' suffix) |
| Mounting Type | Surface Mount | Surface Mount |
| Speed Grade | -10 | β |
| Logic Technology | CMOS | β |
| Configuration Retention | Non-volatile (EEPROM) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant (per lead-free PQFP package marking) |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Series | β | MAX 7000S |
| Family | β | MAX 7000 |
| Architecture | β | Second-generation MAX (CMOS, EEPROM) |
| Logic Elements / Macrocells | β | 192 macrocells |
| Usable Gates | β | 3.75K (typical) |
| User I/Os | β | 124 |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Maximum Internal Frequency | β | 167 MHz |
| Supply Voltage (VCCINT) | β | 5.0 V |
| Supply Voltage (VCCIO) | β | 5.0 V |
| In-System Programmability | β | Yes (5V ISP, JTAG) |
| Boundary-Scan Support | β | IEEE 1149.1 (JTAG) |
| Technology | β | 5V CMOS, EEPROM configuration memory |
| Propagation Delay | β | 7.5 ns to 10 ns (speed grade dependent) |