EPM7256AEFC100-10N vs EPM7256AETC100-5N Comparison
Detailed side-by-side comparison of EPM7256AEFC100-10N by Altera and EPM7256AETC100-5N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7256AEFC100-10N - MAX 7000 CPLD, 256 Macro, 10ns, 100-FBGA | Altera
EPM7256AEFC100-10N NrndAltera
EPM7256AETC100-5N - 256-Macro MAX 7000A CPLD, 5ns TQFP-100
EPM7256AETC100-5N β Last Time BuySpecification Comparison
| Parameter | EPM7256AEFC100-10N | EPM7256AETC100-5N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $24.50 | $9.75 |
| Manufacturer | Altera (now Intel) | β |
| Series | MAX 7000A | MAX 7000AE |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 256 | β |
| Logic Array Blocks (LABs) | 16 | 16 |
| User I/O | 84 | β |
| Number of Gates | 5000 | β |
| Propagation Delay (tPD) | 10 ns | β |
| Maximum Frequency (fMAX) | 154.8 MHz | β |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Tolerance | 5 V tolerant (multiVolt I/O) | β |
| Programmability | EEPROM, In-System Programmable (JTAG IEEE 1149.1) | β |
| Package | 100-LBGA (11 x 11 mm), FineLine BGA | TQFP-100 (1.0 mm pitch, 14x14 mm) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0Β°C to +70Β°C (commercial) | 0C to +70C (Commercial) |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant (lead-free) |
| Process Technology | 0.30 Β΅m EEPROM CMOS | CMOS, EEPROM-based |
| Family | β | MAX 7000A |
| Macro Cells | β | 256 |
| Usable Gates | β | 5000 (range 600 to 10000) |
| User I/Os | β | 84 |
| Pin-to-Pin Delay (tPD) | β | 5.0 ns |
| Counter Frequency (fCNT) | β | up to 227.3 MHz |
| MultiVolt I/O Support | β | 2.5 V / 3.3 V / 5.0 V |
| Program Memory | β | Internal EEPROM |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG) |
| MSL Level | β | 3 (168 hours) |
| Security Bit | β | Programmable |