EPM7256AETC100-5N vs EPM7128AETC100-5N Comparison
Detailed side-by-side comparison of EPM7256AETC100-5N by Altera and EPM7128AETC100-5N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7256AETC100-5N
EPM7256AETC100-5N - 256-Macro MAX 7000A CPLD, 5ns TQFP-100
EPM7256AETC100-5N β Last Time BuyIntel
EPM7128AETC100-5N
EPM7128AETC100-5N - 128-Macrocell MAX 7000A CPLD, 5ns | Intel / Altera
EPM7128AETC100-5N β ActiveSpecification Comparison
| Parameter | EPM7256AETC100-5N | EPM7128AETC100-5N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $6.85 |
| Family | MAX 7000A | MAX 7000A |
| Series | MAX 7000AE | β |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 256 | β |
| Usable Gates | 5000 (range 600 to 10000) | β |
| User I/Os | 84 | 84 |
| Logic Array Blocks (LABs) | 16 | β |
| Pin-to-Pin Delay (tPD) | 5.0 ns | β |
| Counter Frequency (fCNT) | up to 227.3 MHz | β |
| Supply Voltage (VCCINT) | 3.3 V | β |
| MultiVolt I/O Support | 2.5 V / 3.3 V / 5.0 V | β |
| Package | TQFP-100 (1.0 mm pitch, 14x14 mm) | 100-pin TQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Program Memory | Internal EEPROM | β |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | β |
| RoHS Status | Compliant (lead-free) | Compliant |
| MSL Level | 3 (168 hours) | β |
| Process Technology | CMOS, EEPROM-based | β |
| Security Bit | Programmable | β |
| Macrocells | β | 128 |
| Logic Gates (typical) | β | 2,500 |
| Pin-to-Pin Logic Delay (tPD) | β | 5 ns |
| Maximum Operating Frequency | β | 192.3 MHz |
| Core Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Bank Supply Voltage (VCCIO) | β | 3.3 V or 2.5 V |
| 5V Tolerant Inputs | β | Yes (when VCCIO = 3.3 V) |
| Programmable Logic Type | β | EEPROM-based, in-system programmable |
| Programming Interface | β | JTAG (IEEE Std. 1149.1) |