EPM7256AETC144-10N vs EPM7256ATI144-10N Comparison
Detailed side-by-side comparison of EPM7256AETC144-10N by Intel and EPM7256ATI144-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7256AETC144-10N
EPM7256AETC144-10N - MAX 7000A 256-Macro CPLD, 10ns TQFP-144 | Intel
EPM7256AETC144-10N ObsoleteAltera
EPM7256ATI144-10N
EPM7256ATI144-10N - 256-Macrocell MAX 7000A CPLD, 144-TQFP | Altera
EPM7256ATI144-10N β Last Time BuySpecification Comparison
| Parameter | EPM7256AETC144-10N | EPM7256ATI144-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.95 | $30.10 |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 5,000 | 5,000 |
| Macro Cells | 256 | β |
| Logic Array Blocks | 16 | β |
| Maximum User I/O Pins | 120 (in 144-pin TQFP) | β |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | β |
| Maximum Internal Frequency | 95.2 MHz | 93.5 MHz |
| Supply Voltage (Core) | 3.3 V | β |
| I/O Voltage Tolerance | 5 V-tolerant | β |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | β |
| Programming Interface | IEEE 1149.1 JTAG (ISP) | β |
| Package | TQFP-144 (ETC suffix) | TQFP-144 |
| Mounting Type | Surface Mount | β |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Technology | CMOS, EEPROM-based | β |
| Pin Compatibility | Pin-compatible with 5.0V MAX 7000S family | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance per datasheet] |
| Macrocells | β | 256 |
| Logic Array Blocks (LABs) | β | 16 |
| User I/O Pins | β | [DATA_NEEDED: I/O count for 144-pin TQFP variant] |
| Pin-to-Pin Delay | β | 10 ns |
| Supply Voltage VCCINT | β | 3.3 V |
| MultiVolt I/O Voltage VCCIO | β | 2.5 V or 3.3 V |
| Programming Method | β | IEEE Std. 1149.1 JTAG (ISP) |
| Non-volatile Configuration | β | Yes (EEPROM) |