EPM7256EGC192-12 vs EPM7256EGI192-15 Comparison
Detailed side-by-side comparison of EPM7256EGC192-12 by Intel and EPM7256EGI192-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7256EGC192-12 | EPM7256EGI192-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.85 | $52.00 |
| Family | MAX 7000 | MAX 7000 |
| Device Logic Cells | 256 macrocells | β |
| Usable Gates | 5,000 | 5,000 |
| Propagation Delay (tPD) | 12 ns | β |
| Maximum Operating Frequency | 90.9 MHz | 76.9 MHz |
| User I/O Pins | 164 | 192 |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Package | 192-pin CPGA (Ceramic Pin Grid Array) | 192-pin CPGA (Ceramic Pin Grid Array) |
| Mounting Type | Through Hole (PGA socket) | Through-Hole (Socket) |
| Technology | CMOS, EEPROM-based | β |
| Operating Temperature | 0C to +70C (commercial) | β |
| Programmable Interface | JTAG (IEEE 1149.1) / ISP | β |
| Logic Blocks (LABs) | 16 | β |
| Macrocells per LAB | 16 | β |
| RoHS Status | Compliant | Non-compliant (ceramic CPGA, contains lead) |
| Lead-Free | Yes | β |
| JEDEC Package Code | S-CPGA-P192 | β |
| Series | β | MAX 7000E |
| Macro Cells | β | 256 |
| Logic Array Blocks (LABs) | β | 16 |
| Pin-to-Pin Delay (tPD) | β | 15 ns |
| Dedicated Input Pins | β | 12 |
| Programmable Power Mode | β | Yes (per-macrocell) |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG) |
| Configuration Memory | β | EEPROM (non-volatile) |
| Operating Temperature Grade | β | Industrial (-40C to +85C) |