EPM7256SQC208-7 vs EPM7256SQI208-10 Comparison

Detailed side-by-side comparison of EPM7256SQC208-7 by Altera and EPM7256SQI208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM7256SQC208-7

EPM7256SQC208-7 - 256 Macrocell 5V CPLD | Altera | 208-PQFP

EPM7256SQC208-7 Nrnd
Altera
EPM7256SQI208-10

EPM7256SQI208-10 - MAX 7000 CPLD 256 Macrocell 10ns | Altera

EPM7256SQI208-10 Nrnd

Specification Comparison

Parameter EPM7256SQC208-7 EPM7256SQI208-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $0.40
Device Family MAX 7000S (EPM7256S) MAX 7000 (EPM7256)
Macrocells 256 256
Usable Gates 5,000 5000
User I/O Pins 164 β€”
Propagation Delay (tPD) 7.5 ns 10 ns
Maximum Operating Frequency (fMAX) 128.2 MHz β€”
Supply Voltage (VCC) 5.0 V β€”
Configuration Technology EEPROM (non-volatile) β€”
In-System Programmability Yes (IEEE 1149.1 JTAG) β€”
Package 208-pin PQFP (28 x 28 mm, 0.5 mm pitch) 208-pin PQFP (QFP208)
Mounting Type Surface Mount Surface Mount
Operating Temperature Range Commercial (0C to +70C) -40 C to +85 C (Industrial)
Minimum DC Input Voltage -0.5 V β€”
Input Undershoot Tolerance -2.0 V for <100 mA, <20 ns β€”
Speed Grade -7 (7.5 ns) β€”
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
MSL Level [DATA_NEEDED: MSL level] β€”
Logic Levels 5.0 V CMOS/TTL compatible β€”
Logic Array Blocks β€” 16
Maximum User I/O Pins β€” 164
Supply Voltage Range β€” 4.5 V to 5.5 V
Technology β€” CMOS EEPROM
Configuration Memory β€” EEPROM (non-volatile)
In-System Programmable β€” Yes (IEEE 1149.1 JTAG)
Package Body Material β€” Plastic/Epoxy
Terminal Form β€” Gull Wing
JESD-30 Package Code β€” S-PQFP-G208
JESD-609 Terminal Finish Code β€” E3

Datasheets & Resources

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